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"顏金泰"
Showing items 56-80 of 100 (4 Page(s) Totally)
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| 中華大學 |
2007 |
Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity Analysis for Signal Integrity
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Feasible Assignment of Wire-Bonding Power Pads in Hierarchical Power Quad-Grids for Signal Integrity
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Routability-Driven Track Routing for Coupling Capacitance Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
具有反面晶片技術的晶片與封裝共構繞線發展(I)
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顏金泰 |
| 中華大學 |
2006 |
Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Optimal Network Analysis in Hierarchical Power Quad-Grids
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Width and Timing-Constrained Wire Sizing for Critical Area Minimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Multilevel Timing-Constrained Full-Chip Routing in Hierarchical Quad-Grid Model
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Floorplan-Aware Decoupling Capacitance Budgeting on Equivalent Circuit Model
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Area-Driven White Space Distribution for Detailed Floorplan Design
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
OPC-Aware Routing Reconstruction for OPE Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Timing-Constrained Yield-Driven Wire Sizing for Critical Area Minimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
可避免干擾雜訊的SOC晶片繞線系統的開發
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顏金泰 |
| 中華大學 |
2006 |
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Constrained Construction of Flexibility-Driven Routing Trees
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Simultaneous Wiring and Buffer Block Planning for Interconnect-Driven Floorplanning
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Constrained Flexibility-Driven Routing Tree Construction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids
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顏金泰; YAN, JIN-TAI |
Showing items 56-80 of 100 (4 Page(s) Totally)
<< < 1 2 3 4 > >>
View [10|25|50] records per page
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