|
English
|
正體中文
|
简体中文
|
0
|
|
???header.visitor??? :
51250626
???header.onlineuser??? :
857
???header.sponsordeclaration???
|
|
|
|
???tair.name??? >
???browser.page.title.author???
|
"顏金泰"???jsp.browse.items-by-author.description???
Showing items 46-55 of 100 (10 Page(s) Totally)
<< < 1 2 3 4 5 6 7 8 9 10 > >>
View [10|25|50] records per page
| 中華大學 |
2008 |
Electromigration-aware Rectilinear Steiner Tree Construction for Analog Circuits
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Simultaneous Assignment of Power Pads and Wires for Reliability-Driven Hierarchical Power Quad-Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Multi-Layer Steiner Tree Construction with Obstacle Avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Packing-Driven Sliceable Transformation for 3D Floorplan Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Noise-Aware Multiple-Voltage Assignment for gate-Level Power Optimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Steiner Tree Construction for Three-Dimensional ICs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Flexible Escape Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Constrained Redundant Via Insertion for Yield Optimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Top-Down-Based Timing-Driven Steiner Tree Construction with Wire Sizing and Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
Showing items 46-55 of 100 (10 Page(s) Totally)
<< < 1 2 3 4 5 6 7 8 9 10 > >>
View [10|25|50] records per page
|
