|
English
|
正體中文
|
简体中文
|
总笔数 :2853524
|
|
造访人次 :
45213915
在线人数 :
803
教育部委托研究计画 计画执行:国立台湾大学图书馆
|
|
|
"顏金泰"的相关文件
显示项目 6-15 / 100 (共10页)
1 2 3 4 5 6 7 8 9 10 > >>
每页显示[10|25|50]项目
| 中華大學 |
2013 |
Post-Layout Redundant Wire Insertion for Fixing Min-Delay Violations
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Resource-Constrained Link Insertion for Delay Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Efficient Assignment of Inter-Die Signals for Die-Stacking SiP Design
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Utilization of Multi-Bit Flip-Flops for Clock Power Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Density-Reduction-Oriented Layer Assignment for Rectangle Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Top-Down-Based Symmetrical Buffered Clock Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Post-Layout OPE-Predicted Redundant Wire Insertion for Clock Skew Minimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Direction-Constrained Layer Assignment for Rectangle Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
IO Connection Assignment and RDL Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
显示项目 6-15 / 100 (共10页)
1 2 3 4 5 6 7 8 9 10 > >>
每页显示[10|25|50]项目
|
