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"顏金泰"

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Showing items 6-15 of 100  (10 Page(s) Totally)
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Institution Date Title Author
中華大學 2013 Post-Layout Redundant Wire Insertion for Fixing Min-Delay Violations 顏金泰; YAN, JIN-TAI
中華大學 2012 New Optimal Layer Assignment for Bus-Oriented Escape Routing 顏金泰; YAN, JIN-TAI
中華大學 2012 Resource-Constrained Link Insertion for Delay Reduction 顏金泰; YAN, JIN-TAI
中華大學 2012 Efficient Assignment of Inter-Die Signals for Die-Stacking SiP Design 顏金泰; YAN, JIN-TAI
中華大學 2012 Utilization of Multi-Bit Flip-Flops for Clock Power Reduction 顏金泰; YAN, JIN-TAI
中華大學 2012 Density-Reduction-Oriented Layer Assignment for Rectangle Escape Routing 顏金泰; YAN, JIN-TAI
中華大學 2012 Top-Down-Based Symmetrical Buffered Clock Routing 顏金泰; YAN, JIN-TAI
中華大學 2012 Post-Layout OPE-Predicted Redundant Wire Insertion for Clock Skew Minimization 顏金泰; YAN, JIN-TAI
中華大學 2012 Direction-Constrained Layer Assignment for Rectangle Escape Routing 顏金泰; YAN, JIN-TAI
中華大學 2011 IO Connection Assignment and RDL Routing for Flip-Chip Designs 顏金泰; YAN, JIN-TAI

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