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教育部委托研究计画 计画执行:国立台湾大学图书馆
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"顏金泰"的相关文件
显示项目 61-85 / 100 (共4页)
<< < 1 2 3 4 > >>
每页显示[10|25|50]项目
| 中華大學 |
2007 |
具有反面晶片技術的晶片與封裝共構繞線發展(I)
|
顏金泰 |
| 中華大學 |
2006 |
Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Optimal Network Analysis in Hierarchical Power Quad-Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Width and Timing-Constrained Wire Sizing for Critical Area Minimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Multilevel Timing-Constrained Full-Chip Routing in Hierarchical Quad-Grid Model
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Floorplan-Aware Decoupling Capacitance Budgeting on Equivalent Circuit Model
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Area-Driven White Space Distribution for Detailed Floorplan Design
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
OPC-Aware Routing Reconstruction for OPE Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Timing-Constrained Yield-Driven Wire Sizing for Critical Area Minimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
可避免干擾雜訊的SOC晶片繞線系統的開發
|
顏金泰 |
| 中華大學 |
2006 |
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Constrained Construction of Flexibility-Driven Routing Trees
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Simultaneous Wiring and Buffer Block Planning for Interconnect-Driven Floorplanning
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Constrained Flexibility-Driven Routing Tree Construction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Sliceable Transformation of Non-Slicing Floorplans Based on Vacant Block Insertion in LB-packing Process
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction with Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
LB-Packing-Based Floorplan Design on DBL Representation
|
顏金泰; YAN, JIN-TAI |
显示项目 61-85 / 100 (共4页)
<< < 1 2 3 4 > >>
每页显示[10|25|50]项目
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