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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"顏金泰"的相關文件
顯示項目 76-100 / 100 (共2頁)
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每頁顯示[10|25|50]項目
| 中華大學 |
2005 |
Timing-Constrained Construction of Flexibility-Driven Routing Trees
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Simultaneous Wiring and Buffer Block Planning for Interconnect-Driven Floorplanning
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Constrained Flexibility-Driven Routing Tree Construction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Sliceable Transformation of Non-Slicing Floorplans Based on Vacant Block Insertion in LB-packing Process
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction with Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
LB-Packing-Based Floorplan Design on DBL Representation
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Floorplan-Aware Steiner Tree Reconstruction for Optimal Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Optimal Shielding Insertion for Inductive Noise Avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
具有訊號完整性的SOC晶片電源供應系統設計
|
顏金泰 |
| 中華大學 |
2004 |
Timing-Constrained Congestion-Driven Global Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2004 |
Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2004 |
Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2004 |
Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2004 |
Double Bound List: A Dynamic Contour-Based Compacted Representation of Non-Slicing Floorplans on LB-Packing Solution Model
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2004 |
A Simulated-Annealing-Based Approach for Timing-Constrained Flexibility-Driven Routing Tree Construction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2003 |
Optimal Wire Sizing for DME-Based Zero-Skew Clock Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2003 |
Congestion-Driven Global Routing Based on Timing-Constrained Routing Flexibilities
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2003 |
先進製程下的可繞性及效能導向SOC繞線系統的開發(I)
|
顏金泰 |
| 中華大學 |
2002 |
SOC晶片實體整合系統的開發
|
顏金泰 |
| 中華大學 |
2001 |
在內建區塊佈局上連線導向完全可繞之緩衝器與線段設定規劃
|
顏金泰 |
| 中華大學 |
2000 |
在深次微米製程上設計有效率之非曼哈坦通道繞線器
|
顏金泰 |
顯示項目 76-100 / 100 (共2頁)
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每頁顯示[10|25|50]項目
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