|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"馮武雄"
Showing items 91-100 of 177 (18 Page(s) Totally) << < 5 6 7 8 9 10 11 12 13 14 > >> View [10|25|50] records per page
| 國立臺灣大學 |
1990 |
An Application of an Expert System in Layout Compaction of VlSI Design
|
Hsiao, P. Y.; 馮武雄; Chen, H. F.; Hsiao, P. Y.; Feng, Wu-Shiung; Chen, H. F. |
| 國立臺灣大學 |
1990 |
Generalized Terminal Connectivity Problem
|
Tsai, C. C.; Chen, S. J.; 馮武雄; Tsai, C. C.; Chen, S. J.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1990 |
New Algorithms Based on Multiple Storage Quadtrees in Hierarchical Compaction of VlSI Mask Layout
|
Hsiao, P. Y.; 馮武雄; Chen, H. F.; Hsiao, P. Y.; Feng, Wu-Shiung; Chen, H. F. |
| 國立臺灣大學 |
1990 |
Using Multiple Storage Quad Tree on a Hierarchical VLSI Compaction Scheme
|
Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1990 |
An Improved Analytical Model of Short Channel MOSFETs Suitable for Circuit Simulation
|
Chow, H. C.; Wang, J. H.; Kuo, J, B.; 馮武雄; Chow, H. C.; Wang, J. H.; Kuo, J, B.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1990 |
Optimal Aspect Ratios of Building Blocks for Floorplan Designs
|
Shih, P. H.; 馮武雄; Shih, P. H.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1990 |
Optimal Aspect Ratios of Building Blocks for Generally Structured VLSI Floorplan Design
|
Shih, P. H.; 馮武雄; Shih, P. H.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1990 |
Via Minimization with Associated Constraints in Three-Layer Routing Problem
|
Fang, S. C.; Chang, K. E.; 馮武雄; Fang, S. C.; Chang, K. E.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1989-12 |
An H-V Tile-Expansion Router
|
Tsai, C. C.; 陳少傑; 馮武雄; Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung |
| 臺大學術典藏 |
1989-12 |
An H-V Tile-Expansion Router
|
Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung; Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung |
Showing items 91-100 of 177 (18 Page(s) Totally) << < 5 6 7 8 9 10 11 12 13 14 > >> View [10|25|50] records per page
|