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Showing items 1-7 of 7 (1 Page(s) Totally)
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| 國立交通大學 |
2019-04-02T06:04:52Z |
Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:56:27Z |
Low-Leakage Bidirectional SCR With Symmetrical Trigger Circuit for ESD Protection in 40-nm CMOS Process
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:55:39Z |
Quad-SCR Device for Cross-Domain ESD Protection
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:48:27Z |
Active ESD Protection for Input Transistors in a 40-nm CMOS Process
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2015-12-02T02:59:12Z |
Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2015-07-21T08:30:57Z |
Power-Rail ESD Clamp Circuit with Embedded-Trigger SCR Device in a 65-nm CMOS Process
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:33:12Z |
Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
Showing items 1-7 of 7 (1 Page(s) Totally)
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