English  |  正體中文  |  简体中文  |  Total items :2850591  
Visitors :  44686789    Online Users :  1058
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
About TAIR

Browse By

News

Copyright

Related Links

"an yeu andy wu"

Return to Browse by Author
Sorting by Title Sort by Date

Showing items 176-185 of 312  (32 Page(s) Totally)
<< < 13 14 15 16 17 18 19 20 21 22 > >>
View [10|25|50] records per page

Institution Date Title Author
臺大學術典藏 2018-09-10T09:22:14Z Networks-on-chip: Architectures, design methodologies, and case studies Chen, S.-J.; Wu, A.-Y.A.; Xu, J.; AN-YEU(ANDY) WU; SAO-JIE CHEN
臺大學術典藏 2018-09-10T08:43:20Z Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon Hsin, H.-K.;Chang, E.-J.;Chao, C.-H.;Lin, S.-Y.;Wu, A.-Y.; Hsin, H.-K.; Chang, E.-J.; Chao, C.-H.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T08:43:20Z Parallel architecture core (PAC)-the first multicore application processor SoC in Taiwan part I: Hardware architecture & software development tools Wu, C.-J.; Lee, J.-K.; Chu, Y.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU; Chang, D.C.-W.;Lin, T.-J.;Wu, C.-J.;Lee, J.-K.;Chu, Y.-H.;Wu, A.-Y.; Chang, D.C.-W.; Lin, T.-J.
臺大學術典藏 2018-09-10T08:43:20Z Parallel architecture core (PAC)-the first multicore application processor SoC in Taiwan part II: Application programming Chen, J.-M.;Liu, C.-N.;Yang, J.-K.;Tseng, S.-Y.;Shih, W.-K.;Wu, A.-Y.; Chen, J.-M.; Liu, C.-N.; Yang, J.-K.; Tseng, S.-Y.; Shih, W.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T08:43:20Z Traffic-and thermal-aware routing for throttled three-dimensional Network-on-Chip systems Lin, S.-Y.;Yin, T.-C.;Wang, H.-Y.;Wu, A.-Y.; Lin, S.-Y.; Yin, T.-C.; Wang, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T08:43:20Z Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems Chao, C.-H.;Yin, T.-C.;Lin, S.-Y.;Wu, A.-Y.; Chao, C.-H.; Yin, T.-C.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T08:43:19Z A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks Chen, K.-C.;Lin, S.-Y.;Shen, W.-C.;Wu, A.-Y.; Chen, K.-C.; Lin, S.-Y.; Shen, W.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T08:43:19Z Adaptive thresholding incorporating temporal and spatial information with eigen-based clutter filter for color Doppler processing in ultrasonic systems Zhan, C.-Z.;Liu, Z.-L.;Wu, A.-Y.; Zhan, C.-Z.; Liu, Z.-L.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T08:43:19Z Design of transport layer assisted routing for thermal-aware 3D Network-on-Chip Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU; Yin, T.-C.;Chao, C.-H.;Lin, S.-Y.;Wu, A.-Y.; Yin, T.-C.; Chao, C.-H.
臺大學術典藏 2018-09-10T08:43:19Z Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders Chao, M.-A.;Shih, X.-Y.;Wu, A.-Y.(A.); Chao, M.-A.; Shih, X.-Y.; Wu, A.-Y.(A.); AN-YEU(ANDY) WU

Showing items 176-185 of 312  (32 Page(s) Totally)
<< < 13 14 15 16 17 18 19 20 21 22 > >>
View [10|25|50] records per page