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Taiwan Academic Institutional Repository >
Browse by Author
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"an yeu andy wu"
Showing items 211-220 of 312 (32 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Computationally efficient fast algorithm and architecture for the IFFT/FFT in DMT/OFDM systems
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Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology
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Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Fast algorithm for reduced-complexity programmable DSP implementation of the IFFT/FFT in DMT systems
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Wu, An-Yeu; Chan, Tsun-Shan; Wang, Bowen; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Optimal fixed-point VLSI structure of a floating-point based digital filter design
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Wu, An-Yeu; Hwang, Kuo-Fuo; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
System architecture of an adaptive reconfigurable DSP computing engine
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Wu, A.-Y.; Liu, K.J.R.; Raghupathy, A.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Overview of ITRI PAC project - From VLIW DSP processor to multicore computing platform
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AN-YEU(ANDY) WU; Wu, A.-Y.; Chu, Y.-H.; Lin, T.-J.; Liu, C.-N.; Tseng, S.-Y. |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Traffic-Balanced IP Mapping Algorithm for 2D-mesh on-chip-networks
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Lin, T.-J.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Traffic-balanced routing algorithm for irregular mesh-based on-chip networks
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Lin, S.-Y.; Huang, C.-H.; Chao, C.-H.; Huang, K.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Algorithm-based low-power and high-performance multimedia signal processing
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Liu, K.J.R.; Wu, A.-Y.; Raghupathy, A.; Chen, J.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
High-performance scheduling algorithm for partially parallel LDPC decoder
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Zhan, C.-Z.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
Showing items 211-220 of 312 (32 Page(s) Totally)
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