| 臺大學術典藏 |
2018-09-10T07:04:42Z |
An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation
|
Rao, H.; Chen, J.; Zhao, V.H.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system
|
Chen, Y.-L.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Cost-effective joint echo-NEXT canceller designs for 10GBase-T ethernet systems based on a shortened impulse response filter (SIRF) scheme
|
Chen, Y.-L.; Hsu, M.-F.; Lai, J.-T.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits
|
Wey, I.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:41Z |
A 7.39mm2 76mw (1944, 972) LDPC decoder chip for IEEE 802.11n applications
|
AN-YEU(ANDY) WU; Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T06:38:03Z |
Reconfigurable color Doppler DSP engine for high-frequency ultrasonic imaging systems
|
T.-H. Yu; S.-Y. Sun; C.-L. Ding; P.-C. Li; A.-Y. (; y) Wu; PAI-CHI LI; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules
|
Ye, J.-J.; Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
On the fixed-point properties of mixed-scaling-rotation cordic algorithm
|
Yu, C.-L.; Yu, T.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
On the new stopping criteria of iterative turbo decoding by using decoding threshold
|
Li, F.-M.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
Robust packet detector based automatic gain control algorithm for OFDM-based ultra-wideband systems
|
Chu, N.-Y.; Lai, J.-T.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
Multilevel LINC system design for power efficiency enhancement
|
Jheng, K.-Y.; Chen, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
A power-aware reconfigurable rendering engine design with 453MPixels/s, 16.4MTriangles/s performance
|
Chao, C.-H.; Kuo, Y.-L.; Wu, A.-Y.; Chien, W.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
A systematic design approach to the band-tracking packet detector in OFDM-based ultrawideband systems
|
Lai, J.-T.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
Ensemble dependent matrix methodology for probabilistic-based fault-tolerant nanoscale circuit design
|
Rao, H.; Chen, J.; Yu, C.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
Joint AGC-equalization algorithm and VLSI architecture for wirelined transceiver designs
|
Lai, J.-T.; Wu, A.-Y.; Lee, C.-H.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement
|
Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system
|
Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A clock-fault tolerant architecture and circuit for reliable nanoelectronics system
|
Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:22:08Z |
Multilevel LINC system design for wireless transmitters
|
Chen, Y.-J.; Jheng, K.-Y.; Wu, A.-Y.; Tsao, H.-W.; Tzeng, B.; HEN-WAI TSAO; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Huang, K.-K.; Lee, Y.-H.; Yu, T.-H. |
| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Ultra low-cost 3.2Gb/s optical-rate reed solomon decoder IC design
|
Hsu, H.-Y.; Yeo, J.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Low-power design methodology for DSP systems using multirate approach
|
Wu, An-Yeu; Ray Liu, K.J.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; AN-YEU(ANDY) WU; Wu, An-Yeu;Ray Liu, K.J.;Zhang, Zhongying;Nakajima, Kazuo;Raghupathy, Arun |
| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Split recursive least-squares: Algorithms, architectures, and applications
|
Wu;A.-Y.;Ray Liu;K.J.; Wu; A.-Y.; Ray Liu; K.J.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
A robust band-tracking packet detector (BT-PD) in OFDM-based ultra-wideband systems
|
Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
A triple-mode MAP/VA IP design for advanced wireless communication systems
|
Lin, C.-H.; Li, F.-M.; Shi, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
DSP engine design for LINC wireless transmitter systems
|
Jheng, K.-Y.; Wang, Y.-C.; Wu, A.-Y.; Tsao, H.-W.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
Multi-symbol-sliced dynamically reconfigurable reed-solomon decoder design based on unified finite-field processing element
|
Hsu, H.-Y.; Yeo, J.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
On-line MSR-cordic VLSI architecture with applications to cost-efficient rotation-based adaptive filtering systems
|
Yu, T.-H.; Yu, C.-L.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:21Z |
A low cost packet detector in OFDM-based ultra-wideband systems
|
Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:21Z |
A Shortened Impulse Response Filter (SIRF) scheme for cost-effective echo canceller design of 10GBase-T ethernet system
|
Hsu, M.-F.; Chen, Y.-L.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:21Z |
A new early termination scheme of iterative turbo decoding using decoding threshold
|
Li, F.-M.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:16Z |
Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:16Z |
Algorithm-based low-power DSP system design: Methodology and verification
|
Wu, An-Yeu;Liu, K.J.Ray;Zhang, Zhongying;Nakajima, Kazuo;Raghupathy, Arun;Liu, Shang-Chieh; Wu, An-Yeu; Liu, K.J.Ray; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:16Z |
Algorithm-based low-power transform coding architectures
|
Wu, An-Yeu;Liu, K.J.Ray; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
A scalable DCO design for portable ADPLL designs
|
Wu, C.-T.; Wang, W.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Digital signal processing engine design for polar transmitter in wireless communication systems
|
Ko, H.-Y.; Wang, Y.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Low cost decision feedback equalizer (DFE) design for giga-bit systems
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A DVB-T baseband demodulator design based on multimode silicon IPs
|
Jheng, K.-Y.; Wu, T.-H.; Wang, Y.-C.; Yeo, J.-C.; Cho, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A high-speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T. |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A memory-reduced Log-MAP kernel for turbo decoder
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Tsai, T.-H. |
| 臺大學術典藏 |
2018-09-10T04:56:07Z |
Algorithms and architectures for split recursive least squares
|
Liu, K.J.Ray;Wu, An-Yeu; Liu, K.J.Ray; Wu, An-Yeu; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:07Z |
Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion
|
Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
Robust decision feedback equalizer design using soft-threshold-based multi-layer detection scheme
|
Lin, C.-H.;Wu, A.-Y.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme
|
Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
Multiplierless multirate decimator / interpolator module generator
|
Jou, S.-J.;Jheng, K.-Y.;Chen, H.-Y.;Wu, A.-Y.; Jou, S.-J.; Jheng, K.-Y.; Chen, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
A design flow for multiplierless linear-phase fir filters: From system specification to verilog code
|
Jheng, K.-Y.; Jou, S.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design
|
Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
Academia-industry collaboration in SoC design education: Wishes and reality
|
Mashiko, K.; Kanuma, A.; Kozawa, T.; Lee, K.; Wu, A.; Wang, Z.; AN-YEU(ANDY) WU |
