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Showing items 271-280 of 312  (32 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2018-09-10T04:56:06Z High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:06Z Multiplierless multirate decimator / interpolator module generator Jou, S.-J.;Jheng, K.-Y.;Chen, H.-Y.;Wu, A.-Y.; Jou, S.-J.; Jheng, K.-Y.; Chen, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:05Z A design flow for multiplierless linear-phase fir filters: From system specification to verilog code Jheng, K.-Y.; Jou, S.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:05Z A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:05Z Academia-industry collaboration in SoC design education: Wishes and reality Mashiko, K.; Kanuma, A.; Kozawa, T.; Lee, K.; Wu, A.; Wang, Z.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:05Z Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:33:32Z Editorial Wu, A.-Y.A.; Koc, U.-V.; Parhi, K.K.; Theodoridis, S.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:33:32Z Implementation of a programmable 64?2048-point FFT/IFFT processor for OFDM-based communication systems Kuo, J.-C.; Wen, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:33:32Z Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-perforance rotatioal operations Lin, Z.-X.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:33:32Z Multi-layer 2-D adaptive filtering architecture based on McClellan transformation Liu, K.J.Ray; Wu, An-Yeu; AN-YEU(ANDY) WU

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