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Taiwan Academic Institutional Repository >
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"an yeu andy wu"
Showing items 301-310 of 312 (32 Page(s) Totally)
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| 元智大學 |
2011-12-12 |
0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards
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Cheng-Hung Lin; Chun-Yu Chen; En-Jui Chang; An-Yeu (Andy) Wu |
| 元智大學 |
2011-12-12 |
0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards
|
Cheng-Hung Lin; Chun-Yu Chen; En-Jui Chang; An-Yeu (Andy) Wu |
| 臺大學術典藏 |
2011 |
Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding
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Lin, C.-H.;Chen, C.-Y.;Wu, A.-Y.; Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2009 |
A channel-adaptive early termination strategy for LDPC decoders
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Chen, Y.-H.;Chen, Y.-J.;Shih, X.-Y.;Wu, A.-Y.; Chen, Y.-H.; Chen, Y.-J.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2009 |
Welcome message from An-Yeu Wu, conference co-chair
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Wu, A.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2008 |
A universal look-ahead algorithm for pipelining IIR filters
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Chen, Y.-L.; Chen, C.-Y.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2008 |
Unified Convolutional/Turbo decoder design using tile-based timing analysis of VA/MAP kernel
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AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Li, F.-M. |
| 臺大學術典藏 |
2007 |
A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network
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Shen, W.-T.; Chao, C.-H.; Lien, Y.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2006 |
A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment
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Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2006 |
High-performance VLSI architecture of decision feedback equalizer for gigabit systems
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Lin, C.-H.; Wu, A.-Y.; Li, F.-M.; AN-YEU(ANDY) WU |
Showing items 301-310 of 312 (32 Page(s) Totally)
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