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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"an yeu andy wu"的相關文件
顯示項目 306-312 / 312 (共32頁) << < 23 24 25 26 27 28 29 30 31 32 > >> 每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2008 |
A universal look-ahead algorithm for pipelining IIR filters
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Chen, Y.-L.; Chen, C.-Y.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2008 |
Unified Convolutional/Turbo decoder design using tile-based timing analysis of VA/MAP kernel
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AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Li, F.-M. |
| 臺大學術典藏 |
2007 |
A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network
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Shen, W.-T.; Chao, C.-H.; Lien, Y.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2006 |
A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment
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Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2006 |
High-performance VLSI architecture of decision feedback equalizer for gigabit systems
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Lin, C.-H.; Wu, A.-Y.; Li, F.-M.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2001 |
Cost-efficient multiplier-less FIR filter structure based on modified decor transformation
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Lee, I.-H.; Wu, C.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
1996 |
Parallel programmable video co-processor design
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Wu, An-Yeu; Ray Liu, K.J.; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU; Wu, An-Yeu;Ray Liu, K.J.;Raghupathy, Arun;Liu, Shang-Chieh |
顯示項目 306-312 / 312 (共32頁) << < 23 24 25 26 27 28 29 30 31 32 > >> 每頁顯示[10|25|50]項目
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