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Showing items 236-245 of 312  (32 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2018-09-10T06:31:54Z Multilevel LINC system design for power efficiency enhancement Jheng, K.-Y.; Chen, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T06:31:53Z A power-aware reconfigurable rendering engine design with 453MPixels/s, 16.4MTriangles/s performance Chao, C.-H.; Kuo, Y.-L.; Wu, A.-Y.; Chien, W.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T06:31:53Z A systematic design approach to the band-tracking packet detector in OFDM-based ultrawideband systems Lai, J.-T.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T06:31:53Z Ensemble dependent matrix methodology for probabilistic-based fault-tolerant nanoscale circuit design Rao, H.; Chen, J.; Yu, C.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T06:31:53Z Joint AGC-equalization algorithm and VLSI architecture for wirelined transceiver designs Lai, J.-T.; Wu, A.-Y.; Lee, C.-H.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T06:31:52Z A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T06:31:52Z A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T06:31:52Z A clock-fault tolerant architecture and circuit for reliable nanoelectronics system Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T06:22:08Z Multilevel LINC system design for wireless transmitters Chen, Y.-J.; Jheng, K.-Y.; Wu, A.-Y.; Tsao, H.-W.; Tzeng, B.; HEN-WAI TSAO; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T05:59:23Z Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems AN-YEU(ANDY) WU; Wu, A.-Y.; Huang, K.-K.; Lee, Y.-H.; Yu, T.-H.

Showing items 236-245 of 312  (32 Page(s) Totally)
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