| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Ultra low-cost 3.2Gb/s optical-rate reed solomon decoder IC design
|
Hsu, H.-Y.; Yeo, J.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Low-power design methodology for DSP systems using multirate approach
|
Wu, An-Yeu; Ray Liu, K.J.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; AN-YEU(ANDY) WU; Wu, An-Yeu;Ray Liu, K.J.;Zhang, Zhongying;Nakajima, Kazuo;Raghupathy, Arun |
| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Split recursive least-squares: Algorithms, architectures, and applications
|
Wu;A.-Y.;Ray Liu;K.J.; Wu; A.-Y.; Ray Liu; K.J.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
A robust band-tracking packet detector (BT-PD) in OFDM-based ultra-wideband systems
|
Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
A triple-mode MAP/VA IP design for advanced wireless communication systems
|
Lin, C.-H.; Li, F.-M.; Shi, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
DSP engine design for LINC wireless transmitter systems
|
Jheng, K.-Y.; Wang, Y.-C.; Wu, A.-Y.; Tsao, H.-W.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
Multi-symbol-sliced dynamically reconfigurable reed-solomon decoder design based on unified finite-field processing element
|
Hsu, H.-Y.; Yeo, J.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
On-line MSR-cordic VLSI architecture with applications to cost-efficient rotation-based adaptive filtering systems
|
Yu, T.-H.; Yu, C.-L.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:21Z |
A low cost packet detector in OFDM-based ultra-wideband systems
|
Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:21Z |
A Shortened Impulse Response Filter (SIRF) scheme for cost-effective echo canceller design of 10GBase-T ethernet system
|
Hsu, M.-F.; Chen, Y.-L.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:21Z |
A new early termination scheme of iterative turbo decoding using decoding threshold
|
Li, F.-M.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:16Z |
Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:16Z |
Algorithm-based low-power DSP system design: Methodology and verification
|
Wu, An-Yeu;Liu, K.J.Ray;Zhang, Zhongying;Nakajima, Kazuo;Raghupathy, Arun;Liu, Shang-Chieh; Wu, An-Yeu; Liu, K.J.Ray; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:16Z |
Algorithm-based low-power transform coding architectures
|
Wu, An-Yeu;Liu, K.J.Ray; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
A scalable DCO design for portable ADPLL designs
|
Wu, C.-T.; Wang, W.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Digital signal processing engine design for polar transmitter in wireless communication systems
|
Ko, H.-Y.; Wang, Y.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Low cost decision feedback equalizer (DFE) design for giga-bit systems
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A DVB-T baseband demodulator design based on multimode silicon IPs
|
Jheng, K.-Y.; Wu, T.-H.; Wang, Y.-C.; Yeo, J.-C.; Cho, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A high-speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T. |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A memory-reduced Log-MAP kernel for turbo decoder
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Tsai, T.-H. |
| 臺大學術典藏 |
2018-09-10T04:56:07Z |
Algorithms and architectures for split recursive least squares
|
Liu, K.J.Ray;Wu, An-Yeu; Liu, K.J.Ray; Wu, An-Yeu; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:07Z |
Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion
|
Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
Robust decision feedback equalizer design using soft-threshold-based multi-layer detection scheme
|
Lin, C.-H.;Wu, A.-Y.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
