| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Digital signal processing engine design for polar transmitter in wireless communication systems
|
Ko, H.-Y.; Wang, Y.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Low cost decision feedback equalizer (DFE) design for giga-bit systems
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A DVB-T baseband demodulator design based on multimode silicon IPs
|
Jheng, K.-Y.; Wu, T.-H.; Wang, Y.-C.; Yeo, J.-C.; Cho, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A high-speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T. |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A memory-reduced Log-MAP kernel for turbo decoder
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Tsai, T.-H. |
| 臺大學術典藏 |
2018-09-10T04:56:07Z |
Algorithms and architectures for split recursive least squares
|
Liu, K.J.Ray;Wu, An-Yeu; Liu, K.J.Ray; Wu, An-Yeu; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:07Z |
Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion
|
Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
Robust decision feedback equalizer design using soft-threshold-based multi-layer detection scheme
|
Lin, C.-H.;Wu, A.-Y.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme
|
Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
Multiplierless multirate decimator / interpolator module generator
|
Jou, S.-J.;Jheng, K.-Y.;Chen, H.-Y.;Wu, A.-Y.; Jou, S.-J.; Jheng, K.-Y.; Chen, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
A design flow for multiplierless linear-phase fir filters: From system specification to verilog code
|
Jheng, K.-Y.; Jou, S.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design
|
Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
Academia-industry collaboration in SoC design education: Wishes and reality
|
Mashiko, K.; Kanuma, A.; Kozawa, T.; Lee, K.; Wu, A.; Wang, Z.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique
|
Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:32Z |
Editorial
|
Wu, A.-Y.A.; Koc, U.-V.; Parhi, K.K.; Theodoridis, S.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:32Z |
Implementation of a programmable 64?2048-point FFT/IFFT processor for OFDM-based communication systems
|
Kuo, J.-C.; Wen, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:32Z |
Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-perforance rotatioal operations
|
Lin, Z.-X.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:32Z |
Multi-layer 2-D adaptive filtering architecture based on McClellan transformation
|
Liu, K.J.Ray; Wu, An-Yeu; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:31Z |
A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes
|
Wu, Cheng-Shing; Wu, An-Yeu; Lin, Chih-Hsiu; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:31Z |
A novel echo cancellation algorithm and architecture based on multi-part adaptive interpolated FIR filter
|
Wu, C.-S.B.; Wu, A.-Y.A.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:31Z |
A novel multipath matrix algorithm for exact room response identification in stereo echo cancellation
|
Lai, J.-T.; Wu, A.-Y.; Yeh, C.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:31Z |
Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems
|
AN-YEU(ANDY) WU; Chen, P.-H.; Kai-Huang; Hsueh, N.-H.; Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T04:13:19Z |
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
|
Hsu, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:13:19Z |
A unified view for vector rotational CORDIC algorithms and architectures based on angle quantization approach
|
Wu, A.-Y.; Wu, C.-S.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:13:18Z |
A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller
|
Wu, C.-S.; Wu, A.-Y.A.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T03:48:22Z |
An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter
|
Yu, C.-L.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T03:48:21Z |
A novel Trellis-based searching scheme for EEAS-based CORDIC algorithm
|
Wu, C.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T03:30:01Z |
Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem
|
Leu, Jye-Jong; Wu, An-Yeu; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T03:30:01Z |
Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT
|
Wu, Cheng-Shing; Wu, An-Yeu; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2017 |
Low-Complexity Stochastic Gradient Pursuit (SGP) Algorithm and Architecture for Robust Compressive Sensing Reconstruction
|
吳安宇;AN-YEU(ANDY) WU;An-Yeu (Andy) Wu;Nai-Shan Huang;Yi Chen;Yu-Min Lin; Yu-Min Lin; Yi Chen; Nai-Shan Huang; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU; 吳安宇 |
| 臺大學術典藏 |
2017 |
Identification of Atrial Fibrillation by Quantitative Analyses of Fingertip Photoplethysmogram
|
吳安宇;AN-YEU(ANDY) WU;Jiann-Shing Jeng;An-Yeu Wu;Dar-Ming Lai;Jiann-Shing Shieh;Yen-Hung Lin;Shih-Ming Shan;Chi-Sheng Hung;Pei-Wen Huang;Sung-Chun Tang; Sung-Chun Tang; Pei-Wen Huang; Chi-Sheng Hung; Shih-Ming Shan; Yen-Hung Lin; Jiann-Shing Shieh; Dar-Ming Lai; An-Yeu Wu; Jiann-Shing Jeng; AN-YEU(ANDY) WU; 吳安宇 |
| 臺大學術典藏 |
2015-10 |
"Low Memory-Cost Scramble Methods for Constructing Deterministic CS Matrixs
|
AN-YEU(;Y) WU; AN-YEU(; Y) WU; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2014 |
Ant Colony Optimization-Based Fault-Aware Routing in Mesh-based Network-on-Chip Systems
|
Hsien-Kai Hsin;En-Jui Chang;Chia-An Lin;An-Yeu (Andy) Wu; Hsien-Kai Hsin; En-Jui Chang; Chia-An Lin; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU; 吳安宇 |
| 元智大學 |
2013-11-1 |
Reconfigurable parallel turbo decoder design for multiple high-mobility 4G systems
|
Cheng-Hung Lin; Chun-Yu Chen; En-Jui Chang; An-Yeu (Andy) Wu |
| 元智大學 |
2013-11-1 |
Reconfigurable parallel turbo decoder design for multiple high-mobility 4G systems
|
Cheng-Hung Lin; Chun-Yu Chen; En-Jui Chang; An-Yeu (Andy) Wu |
| 元智大學 |
2013-11-1 |
Reconfigurable parallel turbo decoder design for multiple high-mobility 4G systems
|
Cheng-Hung Lin; Chun-Yu Chen; En-Jui Chang; An-Yeu (Andy) Wu |
| 臺大學術典藏 |
2013 |
Low-complexity sinusoidal-assisted EMD (SAEMD) algorithms for solving mode-mixing problems in HHT
|
Shen, W.-C.;Chen, Y.-H.;Wu, A.-Y.; Shen, W.-C.; Chen, Y.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2012 |
Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Hung, H.-S.; Lin, S.-Y.; Chih-Hao; Chen, K.-C.; Chen, K.-C.;Chih-Hao;Lin, S.-Y.;Hung, H.-S.;Wu, A.-Y. |
| 元智大學 |
2011-12-12 |
0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards
|
Cheng-Hung Lin; Chun-Yu Chen; En-Jui Chang; An-Yeu (Andy) Wu |
| 元智大學 |
2011-12-12 |
0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards
|
Cheng-Hung Lin; Chun-Yu Chen; En-Jui Chang; An-Yeu (Andy) Wu |
| 臺大學術典藏 |
2011 |
Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding
|
Lin, C.-H.;Chen, C.-Y.;Wu, A.-Y.; Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2009 |
A channel-adaptive early termination strategy for LDPC decoders
|
Chen, Y.-H.;Chen, Y.-J.;Shih, X.-Y.;Wu, A.-Y.; Chen, Y.-H.; Chen, Y.-J.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2009 |
Welcome message from An-Yeu Wu, conference co-chair
|
Wu, A.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2008 |
A universal look-ahead algorithm for pipelining IIR filters
|
Chen, Y.-L.; Chen, C.-Y.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2008 |
Unified Convolutional/Turbo decoder design using tile-based timing analysis of VA/MAP kernel
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Li, F.-M. |
| 臺大學術典藏 |
2007 |
A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network
|
Shen, W.-T.; Chao, C.-H.; Lien, Y.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2006 |
A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment
|
Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2006 |
High-performance VLSI architecture of decision feedback equalizer for gigabit systems
|
Lin, C.-H.; Wu, A.-Y.; Li, F.-M.; AN-YEU(ANDY) WU |
