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Showing items 1-3 of 3 (1 Page(s) Totally) 1 View [10|25|50] records per page
臺大學術典藏 |
2018-09-10T07:04:42Z |
An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation
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Rao, H.; Chen, J.; Zhao, V.H.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
臺大學術典藏 |
2018-09-10T06:31:53Z |
Ensemble dependent matrix methodology for probabilistic-based fault-tolerant nanoscale circuit design
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Rao, H.; Chen, J.; Yu, C.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; AN-YEU(ANDY) WU |
臺大學術典藏 |
2018-09-10T06:31:52Z |
A clock-fault tolerant architecture and circuit for reliable nanoelectronics system
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Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU |
Showing items 1-3 of 3 (1 Page(s) Totally) 1 View [10|25|50] records per page
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