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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Institution Date Title Author
義守大學 2009-04 A Portable Potentiostat with Molecularly Imprinted Polymeric Electrode for Dopamine Sensing Chun-Yueh Huang;Mei-Hwa Lee;Zong-Huan Wu;Hong-Yi Tseng;Yu-Cheng Huang;Bin-Da Liu;Hung-Yin Lin
國立高雄師範大學 2009 A CMOS-compatible Biological Transducer for Creatinine Detection: MIP-gate ISFET Ruey-Lue Wang;Chen-Fu Lin;Hann-Huei Tsai;Ying-Zong Juang;Yan-Kuin Su;Wang-Long Li;Ruey-Lue Wang;Hung-Yin Lin;Jia-Yu Guo;Tian-Jun Tsai;Bin-Da Liu; 王瑞祿
國立高雄師範大學 2008-06 Electric Characteristics of an On-chip Extended-gate ISFET for Sensing Creatinine Ruey-Lue Wang;Hung-Yin Lin;Tian-Jun Tsai;Chen-Fu Lin;Hann-Huei Tsai;Ying-Zong Juang;Chien-Hsuan Liu;Bin-Da Liu; 王瑞祿
南台科技大學 1995-06 A practical current sensing technique for IDDQ testing 唐經洲; Jing-Jou Tang; Kuen-Jong Lee; Bin-Da Liu
南台科技大學 1995-03 Bulit-in intermediate voltage testing for CMOS circuits Jing-Jou Tang ; Kuen-Jong Lee; Bin-Da Liu; 唐經洲;李昆忠;劉濱達
南台科技大學 1995-01 Performance-Directed Compaction for VLSI Symbolic Layout Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; Ting-Chun Chang;王立洋
南台科技大學 1993-05 Layout compaction with minimized delay bound on timing critical paths Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; Tin-Chung Chang;王立洋; 劉濱達
南台科技大學 1993 Performance-Driven Global Routing Based on Simulated Evolution Lih-Yang Wang; Bin-Da Liu; Yen-Tai Lai; Ming-Yuan Yeh; 王立洋;劉濱達
南台科技大學 1993 A graph-based simplex algorithm for minimizing the layout size andthe delay on timing critical paths Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; Ting-Chun Chang; 王立洋;劉濱達
南台科技大學 1992-07 Neural Nerwork on Two Dimensional IC Layout Compaction Lih-Yang Wang; Kun-Nern Chen; Yen-Tai Lai; Bin-Da Liu;王立洋
南台科技大學 1991 Simultaneous Pin Assignment and Global Routing for Custom VLSI Design Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; 王立洋;劉濱達
南台科技大學 1991 Two-Dimensional Layout Compaction by Neural Optimization Network Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu

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