臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC	G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC	G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO

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