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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Institution Date Title Author
國立交通大學 2018-08-21T05:57:09Z ESD-Induced Latchup-Like Failure in a Touch Panel Control IC Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi
國立交通大學 2017-04-21T06:56:36Z ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi
國立交通大學 2017-04-21T06:49:33Z On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process Ker, Ming-Dou; Chiu, Po-Yen; Tsai, Fu-Yi; Chang, Yeong-Jar
國立交通大學 2015-07-21T08:31:00Z DESIGN OF 2xV(DD) LOGIC GATES WITH ONLY 1xV(DD) DEVICES IN NANOSCALE CMOS TECHNOLOGY Chiu, Po-Yen; Ker, Ming-Dou
國立交通大學 2014-12-12T02:38:13Z 系統單晶片應用之靜電放電箝制電路與輸出緩衝器可靠度設計 邱柏硯; Chiu, Po-Yen; 柯明道; Ker, Ming-Dou
國立交通大學 2014-12-08T15:35:09Z Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit Chiu, Po-Yen; Ker, Ming-Dou
國立交通大學 2014-12-08T15:32:16Z Design of 2 x V-DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 x V-DD Thin-Oxide Devices Ker, Ming-Dou; Chiu, Po-Yen
國立交通大學 2014-12-08T15:28:41Z Failure Analysis on Gate-Driven ESD Clamp Circuit after TLP Stresses of Different Voltage Steps in a 16-V CMOS Process Dai, Chia-Tsen; Chiu, Po-Yen; Ker, Ming-Dou; Tsai, Fu-Yi; Peng, Yan-Hua; Tsai, Chia-Ku
國立交通大學 2014-12-08T15:27:19Z New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process Ker, Ming-Dou; Chiu, Po-Yen
國立交通大學 2014-12-08T15:25:20Z Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process Chiu, Po-Yen; Ker, Ming-Dou; Tsai, Fu-Yi; Chang, Yeong-Jar

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