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Institution	Date	Title	Author
國立臺灣大學	2012	考慮密集資料路徑結構之電路擺置	周昇; Chou, Sheng
國立成功大學	2011-07	An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis	Chou, Sheng; Han, Cheng-Shen; Huang, Po-Kai; Tien, Ko-Fan; Ho, Tsung-Yi

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