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Showing items 26-31 of 31 (2 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:12:02Z |
Parallel Architecture Core (PAC)-the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools
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Chang, David Chih-Wei; Lin, Tay-Jyi; Wu, Chung-Ju; Lee, Jenq-Kuen; Chu, Yuan-Hua; Wu, An-Yeu |
| 國立臺灣大學 |
2010 |
Energy-Efficient Real-Time Scheduling of Multimedia Tasks on Multi-Core Processors
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Wei, Yi-Hung; Yang, Chuan-Yue; Kuo, Tei-Wei; Hung, Shih-Hao; Chu, Yuan-Hua |
| 育達商業科技大學 |
2009 |
Self-Timed Torus Network with 1-of-5 Encoding
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Chang, Yuan-Teng;Huang, Man-Chen;Cheng, Wei-Min;Tsai, Hung-Yue;Chen, Chang-Jiu;Cheng, Fu-Chiung;Chu, Yuan-Hua |
| 淡江大學 |
2005-08-29 |
The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle
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Yang, Wei-bin; Kuo, Shu-chang; Chu, Yuan-hua; Cheng, Kuo-hsing |
| 淡江大學 |
1996-05 |
True-single-phase all-N-logic differential logic (TADL) for very high-speed complex VLSI
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Huang, Hong-yi; 鄭國興; Cheng, Kuo-hsing; Chu, Yuan-hua; Wu, Chung-yu |
| 淡江大學 |
1995-04-30 |
Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits
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Huang, Hong-yi; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan; Chu, Yuan-hua; Wu, Tain-shun; Wu, Chung-yu |
Showing items 26-31 of 31 (2 Page(s) Totally)
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