|
English
|
正體中文
|
简体中文
|
总笔数 :0
|
|
造访人次 :
51955622
在线人数 :
808
教育部委托研究计画 计画执行:国立台湾大学图书馆
|
|
|
"chuang ch"的相关文件
显示项目 21-30 / 57 (共6页)
<< < 1 2 3 4 5 6 > >>
每页显示[10|25|50]项目
| 國立交通大學 |
2014-12-08T15:42:23Z |
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
|
Ker, MD; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:42:10Z |
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
|
Ker, MD; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:38:30Z |
On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
|
Ker, MD; Lin, KH; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:27:05Z |
The electronic structure and optical properties of phosphorus implanted GaN films
|
Shu, CK; Lee, WH; Huang, HY; Chuang, CH; Chen, WK; Chen, WH; Lee, MC |
| 國立交通大學 |
2014-12-08T15:27:01Z |
Effects in carrier dynamics of Isolectronic In doped in GaN films grown by metalorganic vapor phase epitaxy
|
Huang, HY; Shu, CK; Lin, WC; Liao, KC; Chuang, CH; Lee, MC; Chen, WH; Chen, WK; Lee, YY |
| 國立交通大學 |
2014-12-08T15:26:45Z |
ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration
|
Ker, MD; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:26:43Z |
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process
|
Ker, MD; Chuang, CH; Lo, WY |
| 國立交通大學 |
2014-12-08T15:26:38Z |
ESD protection circuits with novel MOS-bounded diode structures
|
Ker, MD; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:26:34Z |
ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
|
Ker, MD; Chuang, CH; Hsu, KC; Lo, WY |
| 國立交通大學 |
2014-12-08T15:26:21Z |
MOS-bounded diodes for on-chip ESD protection in a 0.15-mu m shallow-trench-isolation salicided CMOS process
|
Ker, MD; Lin, KH; Chuang, CH |
显示项目 21-30 / 57 (共6页)
<< < 1 2 3 4 5 6 > >>
每页显示[10|25|50]项目
|
