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"chuang chi nan"
Showing items 1-7 of 7 (1 Page(s) Totally)
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| 國立臺灣大學 |
2009 |
A 20MHz~3GHz wide-range multi-phase delay-locked loop
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Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-10 |
A 3~8GHz delay-locked loop with cycle jitter calibration
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Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration
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Chuang, Chi-Nan; Liu, Shen-Iuan |
| 東吳大學 |
2007 |
銀行帳戶異常交易偵測之研究
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莊啟男; Chuang, Chi-Nan |
| 國立臺灣大學 |
2007 |
A time-constant calibrated phase-locked loop with a fast-locked time
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Han, Sung-Rung; Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump
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Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 1 V Phase Locked Loop with Leakage Compensation in 0.13 ?m CMOS Technology
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CHUANG, Chi-Nan; LIU, Shen-Iuan |
Showing items 1-7 of 7 (1 Page(s) Totally)
1
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