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Taiwan Academic Institutional Repository >
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"chuang ching te"
Showing items 156-205 of 221 (5 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:36:16Z |
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:13Z |
A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist
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Chiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:11Z |
FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientation
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Hu, Vita Pi-Ho; Fan, Ming-Long; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:35:52Z |
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits
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Fan, Ming-Long; Yang, Shao-Yu; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:35:47Z |
Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications
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Huang, Teng-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Chen, Kuan-Neng; Chiou, Jin-Chern; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:46Z |
Low Temperature (< 180 degrees C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration
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Chien, Yu-San; Huang, Yan-Pin; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:35:46Z |
Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications
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Chang, Ming-Hung; Hsieh, Wei-Chih; Wu, Pei-Chen; Chuang, Ching-Te; Chen, Kuan-Neng; Wang, Chen-Chao; Ting, Chun-Yen; Chen, Kua-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:45Z |
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
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Chang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang |
| 國立交通大學 |
2014-12-08T15:35:44Z |
Near-/Sub-V-th Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection
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Chang, Ming-Hung; Lin, Shang-Yuan; Wu, Pei-Chen; Zakoretska, Olesya; Chuang, Ching-Te; Chen, Kuan-Neng; Wang, Chen-Chao; Chen, Kua-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:28Z |
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors
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Wang, Dao-Ping; Lin, Hon-Jarn; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:19Z |
Low-Temperature Bonded Cu/In Interconnect With High Thermal Stability for 3-D Integration
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Chien, Yu-San; Huang, Yan-Pin; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:35:18Z |
Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits
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Yang, Shao-Yu; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:35:16Z |
Low Temperature (< 180 degrees C) Bonding for 3D Integration
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Huang, Yan-Pin; Tzeng, Ruoh-Ning; Chien, Yu-San; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chuang, Ching-Te; Hwang, Wei; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:35:05Z |
A TSV-Based Bio-Signal Package With mu-Probe Array
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Chou, Lei-Chun; Lee, Shih-Wei; Huang, Po-Tsang; Chang, Chih-Wei; Chiang, Cheng-Hao; Wu, Shang-Lin; Chuang, Ching-Te; Chiou, Jin-Chern; Hwang, Wei; Wu, Chung-Hsi; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:33:26Z |
Novel Cu-to-Cu Bonding With Ti Passivation at 180 degrees C in 3-D Integration
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Huang, Yan-Pin; Chien, Yu-San; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chiu, Chi-Tsung; Chiou, Jin-Chern; Chuang, Ching-Te; Hwang, Wei; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:33:15Z |
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM
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Yang, Hao-I.; Yang, Shyh-Chyi; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:43Z |
Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:43Z |
Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs
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Tsai, Ming-Fu; Fan, Ming-Long; Pao, Chia-Hao; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:20Z |
Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:12Z |
Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense Amplifiers
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:12Z |
Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:31:54Z |
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection
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Ghosh, Amlan; Rao, Rahul M.; Kim, Jae-Joon; Chuang, Ching-Te; Brown, Richard B. |
| 國立交通大學 |
2014-12-08T15:31:13Z |
Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:31:09Z |
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices
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Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:49Z |
Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration
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Chiang, Cheng-Hao; Hu, Yu-Chen; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:30:49Z |
Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations
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Hu, Yu-Chen; Chiang, Cheng-Hao; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:30:35Z |
Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nein; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:30Z |
Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:25Z |
Design and Analysis of Robust Tunneling FET SRAM
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Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:07Z |
Testing Strategies for a 9T Sub-threshold SRAM
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Yang, Hao-Yu; Lin, Chen-Wei; Chen, Hung-Hsin; Chao, Mango C. -T.; Tu, Ming-Hsien; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:06Z |
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
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Yang, Hao-I; Lin, Yi-Wei; Hsia, Mao-Chih; Lin, Geng-Cing; Chang, Chi-Shin; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立交通大學 |
2014-12-08T15:30:06Z |
An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array
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Lin, Geng-Cing; Wang, Shao-Cheng; Lin, Yi-Wei; Tsai, Ming-Chien; Chuang, Ching-Te; Jou, Shyh-Jye; Lien, Nan-Chun; Shih, Wei-Chiang; Lee, Kuen-Di; Chu, Jyun-Kai |
| 國立交通大學 |
2014-12-08T15:30:04Z |
Variation Tolerant CLSAs for Nanoscale Bulk-CMOS and FinFET SRAM
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Tsai, Ming-Fu; Tsai, Jen-Huan; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:03Z |
Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAM
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Wang, Shao-Cheng; Lin, Geng-Cing; Lin, Yi-Wei; Tsai, Ming-Chien; Chiu, Yi-Wei; Jou, Shyh-Jye; Chuang, Ching-Te; Lien, Nan-Chun; Shih, Wei-Chiang; Lee, Kuen-Di; Chu, Jyun-Kai |
| 國立交通大學 |
2014-12-08T15:30:03Z |
A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits
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Pao, Chia-Hao; Fan, Ming-Long; Tsai, Ming-Fu; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
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Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:29:40Z |
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:28:05Z |
Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM cell, and Logic Circuits
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:25:40Z |
TIMING CONTROL DEGRADATION AND NBTI/PBTI TOLERANT DESIGN FOR WRITE-REPLICA CIRCUIT IN NANOSCALE CMOS SRAM
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Yang, Shyh-Chyi; Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:24Z |
Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:21Z |
Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold Region
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Fan, Ming-Long; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:25:19Z |
Impact of Gate-Oxide Breakdown on Power-Gated SRAM
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:24:25Z |
Investigation of Static Noise Margin of Ultra-Thin-Body SOI SRAM Cells in Subthreshold Region using Analytical Solution of Poisson's Equation
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Hu, Vita Pi-Ho; Wu, Yu-Sheng; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:23:48Z |
"Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits"
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:23:36Z |
Impacts of NBTI and PBTI on Power-Gated SRAM with High-k Metal-Gate Devices
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:23:33Z |
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs
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Hsieh, Chien-Yu; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:23:26Z |
Modeling, Analysis, and TCAD of Nanoscale Devices and Circuits
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Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:23:11Z |
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
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Tu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Lu, Chien-Yu; Lin, Yuh-Jiun; Wang, Meng-Hsueh; Huang, Huan-Shun; Lee, Kuen-Di; Shih, Wei-Chiang (Willis); Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:21:46Z |
Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI
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Lu, Chien-Yu; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:21:25Z |
Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
Showing items 156-205 of 221 (5 Page(s) Totally)
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