|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"chuang ching te"
Showing items 76-100 of 221 (9 Page(s) Totally)
<< < 1 2 3 4 5 6 7 8 9 > >>
View [10|25|50] records per page
| 國立交通大學 |
2015-11-26T01:02:09Z |
28 奈米高介電係數金屬閘極製程操縱在 近/次臨界電壓之256kb 6T 靜態隨機存取記憶體
|
李光宇; Li, Kuang-Yu; 莊景德; 黃威; Chuang,Ching-Te; Hwang, Wei |
| 國立交通大學 |
2015-11-26T01:02:09Z |
應用於高密度神經感測之低雜訊截波穩定型之開迴路神經訊號放大器
|
黃硯榆; Huang, Yan-Yu; 莊景德; 黃威; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2015-11-26T00:57:08Z |
事件驅動能源控制之高能源效率氣體辨識系統
|
黃羣穎; Huang, Chun-Ying; 黃威; 莊景德; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T11:21:14Z |
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits
|
Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T11:20:58Z |
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
|
Lien, Nan-Chun; Chu, Li-Wei; Chen, Chien-Hen; Yang, Hao-I.; Tu, Ming-Hsien; Kan, Paul-Sen; Hu, Yong-Jyun; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立交通大學 |
2015-07-21T11:20:55Z |
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices
|
Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T11:20:52Z |
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
|
Huang, Po-Tsang; Wu, Shang-Lin; Huang, Yu-Chieh; Chou, Lei-Chun; Huang, Teng-Chieh; Wang, Tang-Hsuan; Lin, Yu-Rou; Cheng, Chuan-An; Shen, Wen-Wei; Chuang, Ching-Te; Chen, Kuan-Neng; Chiou, Jin-Chern; Hwang, Wei; Tong, Ho-Ming |
| 國立交通大學 |
2015-07-21T08:31:30Z |
2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
|
Huang, Po-Tsang; Chou, Lei-Chun; Huang, Teng-Chieh; Wu, Shang-Lin; Wang, Tang-Shuan; Lin, Yu-Rou; Cheng, Chuan-An; Shen, Wen-Wei; Chen, Kuan-Neng; Chiou, Jin-Chern; Chuang, Ching-Te; Hwang, Wei; Chen, Kuo-Hua; Chiu, Chi-Tsung; Cheng, Ming-Hsiang; Lin, Yueh-Lung; Tong, Ho-Ming |
| 國立交通大學 |
2015-07-21T08:31:27Z |
Evaluation of Read-and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:31:17Z |
Energy-Efficient Configurable Discrete Wavelet Transform for Neural Sensing Applications
|
Wang, Tang-Hsuan; Huang, Po-Tsang; Chen, Kuan-Neng; Chiou, Jin-Chem; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2015-07-21T08:31:16Z |
Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer Coupling
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:31:11Z |
Evaluation of Transient Voltage Collapse Write-Assist for GeOI and SOI FinFET SRAM Cells
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:31:00Z |
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
|
Liao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun |
| 國立交通大學 |
2015-07-21T08:30:59Z |
Method for Resolving Simultaneous Same-Row Access In Dual-Port 8T SRAM with Asynchronous Dual-Clock Operation
|
Lien, Nan-Chun; Chuang, Ching-Te; Wu, Wen-Rang |
| 國立交通大學 |
2015-07-21T08:30:58Z |
A Disturb-Free Subthreshold 9T SRAM Cell With Improved Performance and Variation Tolerance
|
Lu, Chien-Yu; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:29:40Z |
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
|
Lu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Ya-Ping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin |
| 國立交通大學 |
2015-07-21T08:29:05Z |
Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Hsu, Chih-Wei; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:29:00Z |
A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
|
Chang, Chih-Wei; Chou, Lei-Chun; Huang, Po-Tsang; Wu, Shang-Lin; Lee, Shih-Wei; Chuang, Ching-Te; Chen, Kuan-Neng; Hwang, Wei; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chiou, Jin-Chern |
| 國立交通大學 |
2015-07-21T08:28:07Z |
Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-16T06:15:25Z |
DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL
|
Chuang Ching-Te; Yang Hao-I; Lin Jihi-Yu; Yang Shyh-Chyi; Tu Ming-Hsien; Hwang Wei; Jou Shyh-Jye; Lee Kun-Ti; Li Hung-Yu |
| 國立交通大學 |
2014-12-16T06:15:18Z |
SCHMITT TRIGGER-BASED FINFET SRAM CELL
|
Chuang Ching-Te; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin |
| 國立交通大學 |
2014-12-16T06:15:18Z |
LOW POWER STATIC RANDOM ACCESS MEMORY
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Hwang Wei; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:15:18Z |
STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Lin Yung-Wei; Lu Chien-Yu; Tu Ming-Hsien; Hwang Wei; Jou Shyh-Jye; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:15:17Z |
DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY
|
Chuang Ching-Te; Yang Hao-I; Lin Yi-Wei; Hwang Wei; Shih Wei-Chiang; Chen Chia-Cheng |
| 國立交通大學 |
2014-12-16T06:15:17Z |
VARIATION-TOLERANT WORD-LINE UNDER-DRIVE SCHEME FOR RANDOM ACCESS MEMORY
|
Chuang Ching-Te; Lin Yi-Wei; Chen Chia-Cheng; Shih Wei-Chiang |
Showing items 76-100 of 221 (9 Page(s) Totally)
<< < 1 2 3 4 5 6 7 8 9 > >>
View [10|25|50] records per page
|
