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"chuang ching te"的相关文件
显示项目 176-221 / 221 (共5页)
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| 國立交通大學 |
2014-12-08T15:32:12Z |
Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:31:54Z |
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection
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Ghosh, Amlan; Rao, Rahul M.; Kim, Jae-Joon; Chuang, Ching-Te; Brown, Richard B. |
| 國立交通大學 |
2014-12-08T15:31:13Z |
Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:31:09Z |
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices
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Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:49Z |
Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration
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Chiang, Cheng-Hao; Hu, Yu-Chen; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:30:49Z |
Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations
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Hu, Yu-Chen; Chiang, Cheng-Hao; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:30:35Z |
Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nein; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:30Z |
Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:25Z |
Design and Analysis of Robust Tunneling FET SRAM
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Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:07Z |
Testing Strategies for a 9T Sub-threshold SRAM
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Yang, Hao-Yu; Lin, Chen-Wei; Chen, Hung-Hsin; Chao, Mango C. -T.; Tu, Ming-Hsien; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:06Z |
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
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Yang, Hao-I; Lin, Yi-Wei; Hsia, Mao-Chih; Lin, Geng-Cing; Chang, Chi-Shin; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立交通大學 |
2014-12-08T15:30:06Z |
An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array
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Lin, Geng-Cing; Wang, Shao-Cheng; Lin, Yi-Wei; Tsai, Ming-Chien; Chuang, Ching-Te; Jou, Shyh-Jye; Lien, Nan-Chun; Shih, Wei-Chiang; Lee, Kuen-Di; Chu, Jyun-Kai |
| 國立交通大學 |
2014-12-08T15:30:04Z |
Variation Tolerant CLSAs for Nanoscale Bulk-CMOS and FinFET SRAM
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Tsai, Ming-Fu; Tsai, Jen-Huan; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:03Z |
Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAM
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Wang, Shao-Cheng; Lin, Geng-Cing; Lin, Yi-Wei; Tsai, Ming-Chien; Chiu, Yi-Wei; Jou, Shyh-Jye; Chuang, Ching-Te; Lien, Nan-Chun; Shih, Wei-Chiang; Lee, Kuen-Di; Chu, Jyun-Kai |
| 國立交通大學 |
2014-12-08T15:30:03Z |
A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits
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Pao, Chia-Hao; Fan, Ming-Long; Tsai, Ming-Fu; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
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Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:29:40Z |
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:28:05Z |
Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM cell, and Logic Circuits
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:25:40Z |
TIMING CONTROL DEGRADATION AND NBTI/PBTI TOLERANT DESIGN FOR WRITE-REPLICA CIRCUIT IN NANOSCALE CMOS SRAM
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Yang, Shyh-Chyi; Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:24Z |
Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:21Z |
Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold Region
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Fan, Ming-Long; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:25:19Z |
Impact of Gate-Oxide Breakdown on Power-Gated SRAM
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:24:25Z |
Investigation of Static Noise Margin of Ultra-Thin-Body SOI SRAM Cells in Subthreshold Region using Analytical Solution of Poisson's Equation
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Hu, Vita Pi-Ho; Wu, Yu-Sheng; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:23:48Z |
"Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits"
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:23:36Z |
Impacts of NBTI and PBTI on Power-Gated SRAM with High-k Metal-Gate Devices
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:23:33Z |
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs
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Hsieh, Chien-Yu; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:23:26Z |
Modeling, Analysis, and TCAD of Nanoscale Devices and Circuits
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Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:23:11Z |
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
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Tu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Lu, Chien-Yu; Lin, Yuh-Jiun; Wang, Meng-Hsueh; Huang, Huan-Shun; Lee, Kuen-Di; Shih, Wei-Chiang (Willis); Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:21:46Z |
Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI
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Lu, Chien-Yu; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:21:25Z |
Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:21:20Z |
Impacts of Single Trap Induced Random Telegraph Noise on FinFET Devices and SRAM Cell Stability
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:21:19Z |
Comprehensive Analysis of UTB GeOI Logic Circuits and 6T SRAM Cells considering Variability and Temperature Sensitivity
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:21:19Z |
A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
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Yang, Hao-I; Yang, Shih-Chi; Hsia, Mao-Chih; Lin, Yung-Wei; Lin, Yi-Wei; Chen, Chien-Hen; Chang, Chi-Shin; Lin, Geng-Cing; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立交通大學 |
2014-12-08T15:20:11Z |
Impacts of NBTI on SRAM Array with Power Gating Structure
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:19:54Z |
Design and Analysis of Ultra-Thin-Body SOI Based Subthreshold SRAM
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Hu, Vita Pi-Ho; Wu, Yu-Sheng; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:19:40Z |
Asymmetrical Write-Assist for Single-Ended SRAM Operation
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Lin, Jihi-Yu; Tu, Ming-Hsien; Tsai, Ming-Chien; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:12:04Z |
FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics
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Hu, Vita Pi-Ho; Fan, Ming-Long; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:12:03Z |
Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability-A Model-Based Approach
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Fan, Ming-Long; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:10:57Z |
Optimal design of triple-gate devices for high-performance and low-power applications
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Chiang, Meng-Hsueh; Lin, Jeng-Nan; Kim, Keunwoo; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:10:02Z |
Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap
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Wei, Lan; Deng, Jie; Chang, Li-Wen; Kim, Keunwoo; Chuang, Ching-Te; Wong, H. -S. Philip |
| 國立交通大學 |
2014-12-08T15:09:50Z |
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics
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Joshi, Rajiv V.; Mukhopadhyay, Saibal; Plass, Donald W.; Chan, Yuen H.; Chuang, Ching-Te; Tan, Yue |
| 國立交通大學 |
2014-12-08T15:09:22Z |
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability
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Bansal, Aditya; Rao, Rahul; Kim, Jae-Joon; Zafar, Sufi; Stathis, James H.; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:08:46Z |
Static Noise Margin of Ultrathin-Body SOI Subthreshold SRAM Cells-An Assessment Based on Analytical Solutions of Poisson's Equation
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Hu, Vita Pi-Ho; Wu, Yu-Sheng; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:08:11Z |
TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability
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Kim, Keunwoo; Kuang, Jente B.; Gebara, Fadi H.; Ngo, Hung C.; Chuang, Ching-Te; Nowka, Kevin J. |
| 國立交通大學 |
2014-12-08T15:06:44Z |
Investigation of Cell Stability and Write Ability of FinFET Subthreshold SRAM Using Analytical SNM Model
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Fan, Ming-Long; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:06:27Z |
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
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Tu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Jou, Shyh-Jye; Chuang, Ching-Te |
显示项目 176-221 / 221 (共5页)
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