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"chuang ching te"的相關文件
顯示項目 126-175 / 221 (共5頁)
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| 國立交通大學 |
2014-12-13T10:49:40Z |
奈米隨機存取記憶體的長時間可靠度劣化現象分析與可容忍此劣化現象之設計
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莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:44:37Z |
奈米互補式金氧半場效電晶體靜態隨機存取記憶體靜態雜訊邊界與負偏壓溫度效應/正偏壓溫度效應之量測與特性化電路結構設計
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莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:41:57Z |
奈米互補式金氧半場效電晶體靜態隨機存取記憶體靜態雜訊邊界與負偏壓溫度效應/正偏壓溫度效應之量測與特性化電路結構設計
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莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:41:48Z |
前瞻多閘極/全包覆閘極、奈米線、及穿隧場效電晶體於靜態隨機存取記憶體、邏輯、類比應用之分析與評估
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莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:36:34Z |
前瞻多閘極/全包覆閘極、奈米線、及穿隧場效電晶體於靜態隨機存取記憶體、邏輯、類比應用之分析與評估
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莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-12T02:45:29Z |
抗變異奈米互補式金氧半導體靜態隨機存取記憶體設計
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盧建宇; Lu, Chien-Yu; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T02:45:16Z |
40奈米製程技術操縱在低電壓的 256Kb 8T 雙埠隨機存取記憶體
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鄭銘慶; Zheng, Ming-Ching; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T02:45:16Z |
穿隧式場效電晶體與鰭式場效電晶體的隨機變異特性於元件及邏輯電路之研究與分析
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陳倩如; Chen, Chien-Ju; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T02:45:02Z |
應用於高密度神經元感測之11位元低電壓面積與功耗最佳化之類比數位轉換器
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楊鈞麟; Yang, Chun-Lin; 莊景德; 黃威; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-12T02:45:02Z |
應用於低功率事件驅動感知平台之超低電壓全數位操控線性穩壓器
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郭裔平; Kuo, Yi-Ping; 黃威; 莊景德; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T02:42:47Z |
低操作電壓奈米級靜態隨機記憶體電路設計
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連南鈞; Lien, Nan-Chun; 吳文榕; 莊景德; Wu, Wen-Rong; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T02:38:26Z |
鍺環繞閘極奈米線金氧半場效電晶體及無接面電晶體、邏輯電路和靜態隨機存取記憶體之研究與分析
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楊邵喻; Yang, Shao-Yu; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T02:38:12Z |
應用於2.5D異質整合生物感測微系統之矽載板資料傳輸
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林毓柔; Lin, Yu-Rou; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T02:38:08Z |
應用於多通道神經感測之可配置小波離散轉換
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王唐瑄; Wang, Tang-Hsuan; 黃 威; 莊景德; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T02:38:01Z |
40奈米製程技術操縱在低操縱電壓的256-Kb 8T 靜態隨機存取記憶體
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張智皓; Chang, Zhi-Hao; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T02:33:13Z |
應用於神經感測之面積與功耗最佳化11位元延遲線輔助之循序漸進式類比數位轉換器
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黃騰頡; Huang, Teng-Chieh; 莊景德; 黃威; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:55:03Z |
40奈米1.0Mb 6T管線化靜態隨機存取記憶體與三步階升壓型字元線和位元線降壓和適應性電壓偵測
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廖偉男; Liao, Wei-Nan; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T01:55:02Z |
奈米尺度多重閘極金氧半場效電晶體之靜態隨機存取記憶體的設計與分析特性
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蔡明甫; Tsai, Ming-Fu; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T01:55:02Z |
鰭狀及三閘極場效電晶體元件、邏輯電路、類比電路和靜態隨機存取記憶體之研究與分析
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包家豪; Pao, Chia-Hao; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T01:46:34Z |
奈米級CMOS靜態隨機存取記憶體之 臨界電壓量測電路
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林耕慶; Lin, Geng-Cing; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T01:46:20Z |
40奈米1.0Mb 6T管線化靜態隨機存取記憶體與步階升壓型字元線和適應性數據感知寫入輔助設計
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張琦昕; Chang, chi-Shin; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T01:37:48Z |
超低功率抗雜訊8T 靜態隨機存取記憶體的設計與實現
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夏茂墀; Hsia, Mao-Chih; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-12T01:37:46Z |
應用於交叉點八電晶體靜態隨機存取記憶體之資料感知動態電源寫入輔助之分析與設計
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林勇維; 莊景德; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:42:37Z |
An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process
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Mukhopadhyay, Saibal; Kim, Keunwoo; Jenkins, Keith A.; Chuang, Ching-Te; Roy, Kaushik |
| 國立交通大學 |
2014-12-08T15:38:27Z |
Evaluation of Static Noise Margin and Performance of 6T FinFET SRAM Cells with Asymmetric Gate to Source/Drain Underlap Devices
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:38:26Z |
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMs
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Hsieh, Chien-Yu; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:38:09Z |
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage
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Mukhopadhyay, Saibal; Rao, Rahul M.; Kim, Jae-Joon; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:37:44Z |
Impacts of gate-oxide breakdown on power-gated SRAM
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Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:58Z |
Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:49Z |
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
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Chiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Chu, Yuan-Hua; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:16Z |
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:13Z |
A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist
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Chiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:11Z |
FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientation
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Hu, Vita Pi-Ho; Fan, Ming-Long; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:35:52Z |
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits
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Fan, Ming-Long; Yang, Shao-Yu; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:35:47Z |
Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications
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Huang, Teng-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Chen, Kuan-Neng; Chiou, Jin-Chern; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:46Z |
Low Temperature (< 180 degrees C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration
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Chien, Yu-San; Huang, Yan-Pin; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:35:46Z |
Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications
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Chang, Ming-Hung; Hsieh, Wei-Chih; Wu, Pei-Chen; Chuang, Ching-Te; Chen, Kuan-Neng; Wang, Chen-Chao; Ting, Chun-Yen; Chen, Kua-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:45Z |
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
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Chang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang |
| 國立交通大學 |
2014-12-08T15:35:44Z |
Near-/Sub-V-th Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection
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Chang, Ming-Hung; Lin, Shang-Yuan; Wu, Pei-Chen; Zakoretska, Olesya; Chuang, Ching-Te; Chen, Kuan-Neng; Wang, Chen-Chao; Chen, Kua-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:28Z |
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors
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Wang, Dao-Ping; Lin, Hon-Jarn; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:19Z |
Low-Temperature Bonded Cu/In Interconnect With High Thermal Stability for 3-D Integration
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Chien, Yu-San; Huang, Yan-Pin; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:35:18Z |
Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits
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Yang, Shao-Yu; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:35:16Z |
Low Temperature (< 180 degrees C) Bonding for 3D Integration
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Huang, Yan-Pin; Tzeng, Ruoh-Ning; Chien, Yu-San; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chuang, Ching-Te; Hwang, Wei; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:35:05Z |
A TSV-Based Bio-Signal Package With mu-Probe Array
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Chou, Lei-Chun; Lee, Shih-Wei; Huang, Po-Tsang; Chang, Chih-Wei; Chiang, Cheng-Hao; Wu, Shang-Lin; Chuang, Ching-Te; Chiou, Jin-Chern; Hwang, Wei; Wu, Chung-Hsi; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:33:26Z |
Novel Cu-to-Cu Bonding With Ti Passivation at 180 degrees C in 3-D Integration
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Huang, Yan-Pin; Chien, Yu-San; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chiu, Chi-Tsung; Chiou, Jin-Chern; Chuang, Ching-Te; Hwang, Wei; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:33:15Z |
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM
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Yang, Hao-I.; Yang, Shyh-Chyi; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:43Z |
Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:43Z |
Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs
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Tsai, Ming-Fu; Fan, Ming-Long; Pao, Chia-Hao; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:20Z |
Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:12Z |
Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense Amplifiers
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Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
顯示項目 126-175 / 221 (共5頁)
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