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Showing items 11-60 of 221 (5 Page(s) Totally)
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| 國立交通大學 |
2018-08-21T05:57:00Z |
An Implantable 128-Channel Wireless Neural-Sensing Microsystem using TSV-Embedded Dissolvable mu-Needle Array and Flexible Interposer
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Huang, Po-Tsang; Huang, Yu-Chieh; Wu, Shang-Lin; Hu, Yu-Chen; Lu, Ming-Wei; Sheng, Ting-Wei; Chang, Fung-Kai; Lin, Chun-Pin; Chang, Nien-Shang; Chen, Hung-Lieh; Chen, Chi-Shi; Duann, Jeng-Ren; Chiu, Tzai-Wen; Hwang, Wei; Chen, Kuan-Neng; Chuang, Ching-Te; Chiou, Jin-Chern |
| 國立交通大學 |
2018-08-21T05:56:55Z |
Ultra-Low Voltage Mixed TFET-MOSFET 8T SRAM Cell
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Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Impacts of Work Function Variation and Line Edge Roughness on Hybrid TFET-MOSFET Monolithic 3D SRAMs
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Wang, Jian-Hao; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Evaluation of Analog Performance of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) MOSFETs
|
Lee, Hung-Yi; Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm Node
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Yu, Chang-Hung; Zheng, Jun-Teng; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Exploration and Evaluation of TCAM with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
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Tu, Meng-Hsuan; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:48Z |
Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing Application
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Chen, Jr-Ming; Huang, Po-Tsang; Wu, Shang-Lin; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:54:15Z |
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
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Wu, Shang-Lin; Li, Kuang-Yu; Huang, Po-Tsang; Hwang, Wei; Tu, Ming-Hsien; Lung, Sheng-Chi; Peng, Wei-Sheng; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:53:58Z |
Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:53:55Z |
An Advanced 2.5-D Heterogeneous Integration Packaging for High-Density Neural Sensing Microsystem
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Hu, Yu-Chen; Huang, Yu-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Chang, Hsiao-Chun; Yang, Yu-Tao; You, Yan-Huei; Chen, Jr-Ming; Huang, Yan-Yu; Lin, Yen-Han; Duann, Jeng-Ren; Chiu, Tzai-Wen; Hwang, Wei; Chuang, Ching-Te; Chiou, Jin-Chern; Chen, Kuan-Neng |
| 國立交通大學 |
2018-08-21T05:53:09Z |
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes
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Huang, Yu-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Hu, Yu-Chen; You, Yan-Huei; Chen, Jr-Ming; Huang, Yan-Yu; Chang, Hsiao-Chun; Lin, Yen-Han; Duann, Jeng-Ren; Chiu, Tzai-Wen; Hwang, Wei; Chen, Kuan-Neng; Chuang, Ching-Te; Chiou, Jin-Chern |
| 國立交通大學 |
2018-01-24T07:42:38Z |
應用於可植入式神經感測微系統之低功率無線資料傳輸
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張峰榿; 莊景德; Chang, Feng-Kai; Chuang, Ching-Te |
| 國立交通大學 |
2018-01-24T07:42:16Z |
應用於高密度神經感測之低功率神經訊號放大器
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何寬倫; 莊景德; 黃威; Ho,Kuan-Lun; Chuang,Ching-Te; Hwang,Wei |
| 國立交通大學 |
2018-01-24T07:42:16Z |
應用於物聯網之28奈米4kb 1寫2讀次臨界施密特觸發器先進先出隨機靜態存取記憶體設計
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曾煥然; 莊景德; 黃威; Tseng, Huan-Jan; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:42:01Z |
28奈米近臨界電壓使用12顆電晶體搭配短反或閘型匹配線之管線化的三態內容可定址記憶體
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陳俊丞; 莊景德; 黃威; Chen, Jyun-Cheng; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:41:57Z |
鰭式場效電晶體與穿隧式場效電晶體於低壓降線性穩壓器應用之探討與分析
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張珈寧; 莊景德; Chang, Chia-Ning; Chuang, Ching-Te |
| 國立交通大學 |
2018-01-24T07:41:37Z |
單層及雙層二維過度金屬硫屬化合物之類比特性及應用於跨導運算放大器之研究與分析
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李泓毅; 莊景德; Lee, Hung-Yi; Chuang, Ching-Te |
| 國立交通大學 |
2018-01-24T07:41:26Z |
鰭狀、穿隧場效電晶體元件於超低功耗靜態隨機存取記憶體、邏輯電路及類比電路應用之設計與分析
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陳盈年; 莊景德; Chen, Yin-Nien; Chuang, Ching-Te |
| 國立交通大學 |
2018-01-24T07:40:22Z |
應用於神經訊號感測微系統之低功耗訊號感測轉換與記憶體電路設計
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吳尚霖; 莊景德; Wu, Shang-Lin; Chuang, Ching-Te |
| 國立交通大學 |
2018-01-24T07:38:55Z |
混合穿隧式場效電晶體與鰭式場效電晶體的三態內容可定址記憶體電路超低壓應用之研究與分析
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杜孟軒; 莊景德; 蘇彬; Tu, Meng-Hsuan; Chuang,Ching-Te; Su,Pin |
| 國立交通大學 |
2018-01-24T07:38:55Z |
實現在 40奈米 CMOS之高密度腦神經訊號處理器
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盛庭偉; 莊景德; Sheng, Ting-Woei; Chuang, Ching-Te |
| 國立交通大學 |
2018-01-24T07:38:55Z |
混合穿隧式場效電晶體與金氧半場效電晶體於單晶三維積體靜態隨機存取記憶體考慮層間電耦合的隨機變異特性之研究及分析
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王建皓; 莊景德; Wang, Jian-Hao; Chuang, Ching-Te |
| 國立交通大學 |
2018-01-24T07:38:30Z |
應用於可植入式生醫感測微系統之高效能無線分級電源管理IC
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呂明維; 莊景德; Lu, Ming-Wei; Chuang Ching-Te |
| 國立交通大學 |
2018-01-24T07:38:01Z |
應用於生醫感測平台之 28 奈米極低功率近/次臨界 先進先出記憶體設計
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徐維伸; 莊景德; 黃威; Hsu, Wei-Shen; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2018-01-24T07:37:55Z |
實現在28奈米製程下0.4V近臨界電壓之三態內容可定址記憶體設計
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詹耘昇; 莊景德; 黃威; Chan, Yun-Sheng; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:56:15Z |
Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:55:34Z |
A 0.35 V, 375 kHz, 5.43 mu W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
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Wu, Shang-Lin; Lu, Chien-Yu; Tu, Ming-Hsien; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:50:15Z |
Integration of Neural Sensing Microsystem with TSV-embedded Dissolvable mu-Needles Array, Biocompatible Flexible Interposer, and Neural Recording Circuits
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Huang, Yu-Chieh; Hu, Yu-Chen; Huang, Po-Tsang; Wu, Shang-Lin; You, Yan-Huei; Chen, Jr-Ming; Huang, Yan-Yu; Chang, Hsiao-Chun; Lin, Yen-Han; Duann, Jeng-Ren; Chiu, Tzai-Wen; Hwang, Wei; Chuang, Ching-Te; Chiou, Jin-Chern; Chen, Kuan-Neng |
| 國立交通大學 |
2017-04-21T06:50:10Z |
Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
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Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:50:10Z |
Energy-Efficient Gas Recognition System with Event-Driven Power Control
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Huang, Chun-Ying; Huang, Po-Tsang; Yang, Chih-Chao; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:50:07Z |
An Ultra-High-Density 256-channel/25mm(2) Neural Sensing Microsystem using TSV-embedded Neural Probes
|
Huang, Yu-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Hui, Yu-Chen; You, Yan-Huei; Chen, Jr-Ming; Huang, Yan-Yu; Chang, Hsiao-Chun; Lin, Yen-Han; Duann, Jeng-Ren; Chiu, Tzai-Wen; Hwang, Wei; Chen, Kuan-Neng; Chuang, Ching-Te; Chiou, Jin-Chern |
| 國立交通大學 |
2017-04-21T06:50:06Z |
A Subthreshold SRAM with Embedded Data-Aware Write-Assist and Adaptive Data-Aware Keeper
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Chiu, Yi-Wei; Hu, Yu-Hao; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:50:05Z |
Investigation of BTI Reliability for Monolithic 3D 6T SRAM with Ultra-thin-body GeOI MOSFETs
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Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:57Z |
Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits
|
Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:47Z |
UTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliability
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Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:42Z |
0.339fJ/bit/search Energy-Efficient TCAM Macro Design in 40nm LP CMOS
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Huang, Po-Tsang; Lai, Shu-Lin; Chuang, Ching-Te; Hwang, Wei; Huang, Jason; Hu, Angelo; Kan, Paul; Jia, Michael; Lv, Kimi; Zhang, Bright |
| 國立交通大學 |
2017-04-21T06:49:40Z |
Impact of NBTI and PBTI in SRAM Bit-cells: Relative Sensitivities and Guidelines for Application-Specific Target Stability/Performance
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Bansal, Aditya; Rao, Rahul; Kim, Jae-Joon; Zafar, Sufi; Stathis, James H.; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:37Z |
Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects
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Kim, Jae-Joon; Rao, Rahul; Mukhopadhyay, Saibal; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:36Z |
Stable High-Density FD/SOI SRAM with Selective Back-Gate Bias Using Dual Buried Oxide
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Kim, Keunwoo; Kuang, Jente B.; Gebara, Fadi; Ngo, Hung C.; Chuang, Ching-Te; Nowka, Kevin J. |
| 國立交通大學 |
2017-04-21T06:49:31Z |
A Precise Negative Bias Temperature Instability Sensor using Slew-Rate Monitor Circuitry
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Ghosh, Amlan; Brown, Richard B.; Rao, Rahul M.; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Stability Optimization of Monolithic 3-D MoS2-n/WSe2-p SRAM Cells for Superthreshold and Near-/Sub-threshold Applications
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness
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Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:05Z |
28nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
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Hsu, Wei-Shen; Huang, Po-Tsang; Wu, Shang-Lin; Chuang, Ching-Te; Hwang, Wei; Tu, Ming-Hsien; Yin, Ming-Yu |
| 國立交通大學 |
2017-04-21T06:49:02Z |
Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:48:57Z |
Polymer TSV Fabrication Scheme with Its Electrical and Reliability Test Vehicle
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Lee, Shih-Wei; Shih, Jian-Yu; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chen, Kuan-Neng |
| 國立交通大學 |
2017-04-21T06:48:49Z |
Pre-Si Estimation and Compensation of SRAM Layout Deficiencies to Achieve Target Performance and Yield
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Bansal, Aditya; Singh, Rama N.; Mukhopadhyay, Saibal; Han, Geng; Heng, Fook-Luen; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:48:32Z |
Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices
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Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:48:29Z |
Low Power Algorithm-Architecture Co-Design of Fast Independent Component Analysis (FICA) for Multi-Gas Sensor Applications
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Yang, Chieh-Chao; Huang, Po-Tsang; Huang, Chun-Ying; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2017-04-21T06:48:28Z |
All Digitally Controlled Linear Voltage Regulator with PMOS Strength Self-Calibration for Ripple Reduction
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Kuo, Yi-Ping; Huang, Po-Tsang; Wu, Chung-Shiang; Liang, Yu-Jie; Chuang, Ching-Te; Chu, Yuan-Hua; Hwang, Wei |
Showing items 11-60 of 221 (5 Page(s) Totally)
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