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Showing items 161-185 of 221  (9 Page(s) Totally)
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Institution Date Title Author
國立交通大學 2014-12-08T15:35:46Z Low Temperature (< 180 degrees C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration Chien, Yu-San; Huang, Yan-Pin; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng
國立交通大學 2014-12-08T15:35:46Z Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications Chang, Ming-Hung; Hsieh, Wei-Chih; Wu, Pei-Chen; Chuang, Ching-Te; Chen, Kuan-Neng; Wang, Chen-Chao; Ting, Chun-Yen; Chen, Kua-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Hwang, Wei
國立交通大學 2014-12-08T15:35:45Z A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist Chang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang
國立交通大學 2014-12-08T15:35:44Z Near-/Sub-V-th Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection Chang, Ming-Hung; Lin, Shang-Yuan; Wu, Pei-Chen; Zakoretska, Olesya; Chuang, Ching-Te; Chen, Kuan-Neng; Wang, Chen-Chao; Chen, Kua-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Hwang, Wei
國立交通大學 2014-12-08T15:35:28Z Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors Wang, Dao-Ping; Lin, Hon-Jarn; Chuang, Ching-Te; Hwang, Wei
國立交通大學 2014-12-08T15:35:19Z Low-Temperature Bonded Cu/In Interconnect With High Thermal Stability for 3-D Integration Chien, Yu-San; Huang, Yan-Pin; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng
國立交通大學 2014-12-08T15:35:18Z Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits Yang, Shao-Yu; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:35:16Z Low Temperature (< 180 degrees C) Bonding for 3D Integration Huang, Yan-Pin; Tzeng, Ruoh-Ning; Chien, Yu-San; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chuang, Ching-Te; Hwang, Wei; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng
國立交通大學 2014-12-08T15:35:05Z A TSV-Based Bio-Signal Package With mu-Probe Array Chou, Lei-Chun; Lee, Shih-Wei; Huang, Po-Tsang; Chang, Chih-Wei; Chiang, Cheng-Hao; Wu, Shang-Lin; Chuang, Ching-Te; Chiou, Jin-Chern; Hwang, Wei; Wu, Chung-Hsi; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chen, Kuan-Neng
國立交通大學 2014-12-08T15:33:26Z Novel Cu-to-Cu Bonding With Ti Passivation at 180 degrees C in 3-D Integration Huang, Yan-Pin; Chien, Yu-San; Tzeng, Ruoh-Ning; Shy, Ming-Shaw; Lin, Teu-Hua; Chen, Kou-Hua; Chiu, Chi-Tsung; Chiou, Jin-Chern; Chuang, Ching-Te; Hwang, Wei; Tong, Ho-Ming; Chen, Kuan-Neng
國立交通大學 2014-12-08T15:33:15Z Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM Yang, Hao-I.; Yang, Shyh-Chyi; Hwang, Wei; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:43Z Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:43Z Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs Tsai, Ming-Fu; Fan, Ming-Long; Pao, Chia-Hao; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:20Z Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:12Z Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense Amplifiers Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:12Z Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:31:54Z Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection Ghosh, Amlan; Rao, Rahul M.; Kim, Jae-Joon; Chuang, Ching-Te; Brown, Richard B.
國立交通大學 2014-12-08T15:31:13Z Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:31:09Z Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te
國立交通大學 2014-12-08T15:30:49Z Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration Chiang, Cheng-Hao; Hu, Yu-Chen; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng
國立交通大學 2014-12-08T15:30:49Z Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations Hu, Yu-Chen; Chiang, Cheng-Hao; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng
國立交通大學 2014-12-08T15:30:35Z Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nein; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:30:30Z Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:30:25Z Design and Analysis of Robust Tunneling FET SRAM Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:30:07Z Testing Strategies for a 9T Sub-threshold SRAM Yang, Hao-Yu; Lin, Chen-Wei; Chen, Hung-Hsin; Chao, Mango C. -T.; Tu, Ming-Hsien; Jou, Shyh-Jye; Chuang, Ching-Te

Showing items 161-185 of 221  (9 Page(s) Totally)
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