| 國立交通大學 |
2015-07-21T11:20:55Z |
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices
|
Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T11:20:52Z |
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
|
Huang, Po-Tsang; Wu, Shang-Lin; Huang, Yu-Chieh; Chou, Lei-Chun; Huang, Teng-Chieh; Wang, Tang-Hsuan; Lin, Yu-Rou; Cheng, Chuan-An; Shen, Wen-Wei; Chuang, Ching-Te; Chen, Kuan-Neng; Chiou, Jin-Chern; Hwang, Wei; Tong, Ho-Ming |
| 國立交通大學 |
2015-07-21T08:31:30Z |
2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
|
Huang, Po-Tsang; Chou, Lei-Chun; Huang, Teng-Chieh; Wu, Shang-Lin; Wang, Tang-Shuan; Lin, Yu-Rou; Cheng, Chuan-An; Shen, Wen-Wei; Chen, Kuan-Neng; Chiou, Jin-Chern; Chuang, Ching-Te; Hwang, Wei; Chen, Kuo-Hua; Chiu, Chi-Tsung; Cheng, Ming-Hsiang; Lin, Yueh-Lung; Tong, Ho-Ming |
| 國立交通大學 |
2015-07-21T08:31:27Z |
Evaluation of Read-and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:31:17Z |
Energy-Efficient Configurable Discrete Wavelet Transform for Neural Sensing Applications
|
Wang, Tang-Hsuan; Huang, Po-Tsang; Chen, Kuan-Neng; Chiou, Jin-Chem; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2015-07-21T08:31:16Z |
Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer Coupling
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:31:11Z |
Evaluation of Transient Voltage Collapse Write-Assist for GeOI and SOI FinFET SRAM Cells
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:31:00Z |
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
|
Liao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun |
| 國立交通大學 |
2015-07-21T08:30:59Z |
Method for Resolving Simultaneous Same-Row Access In Dual-Port 8T SRAM with Asynchronous Dual-Clock Operation
|
Lien, Nan-Chun; Chuang, Ching-Te; Wu, Wen-Rang |
| 國立交通大學 |
2015-07-21T08:30:58Z |
A Disturb-Free Subthreshold 9T SRAM Cell With Improved Performance and Variation Tolerance
|
Lu, Chien-Yu; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:29:40Z |
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
|
Lu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Ya-Ping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin |
| 國立交通大學 |
2015-07-21T08:29:05Z |
Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Hsu, Chih-Wei; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:29:00Z |
A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
|
Chang, Chih-Wei; Chou, Lei-Chun; Huang, Po-Tsang; Wu, Shang-Lin; Lee, Shih-Wei; Chuang, Ching-Te; Chen, Kuan-Neng; Hwang, Wei; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chiou, Jin-Chern |
| 國立交通大學 |
2015-07-21T08:28:07Z |
Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-16T06:15:25Z |
DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL
|
Chuang Ching-Te; Yang Hao-I; Lin Jihi-Yu; Yang Shyh-Chyi; Tu Ming-Hsien; Hwang Wei; Jou Shyh-Jye; Lee Kun-Ti; Li Hung-Yu |
| 國立交通大學 |
2014-12-16T06:15:18Z |
SCHMITT TRIGGER-BASED FINFET SRAM CELL
|
Chuang Ching-Te; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin |
| 國立交通大學 |
2014-12-16T06:15:18Z |
LOW POWER STATIC RANDOM ACCESS MEMORY
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Hwang Wei; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:15:18Z |
STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Lin Yung-Wei; Lu Chien-Yu; Tu Ming-Hsien; Hwang Wei; Jou Shyh-Jye; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:15:17Z |
DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY
|
Chuang Ching-Te; Yang Hao-I; Lin Yi-Wei; Hwang Wei; Shih Wei-Chiang; Chen Chia-Cheng |
| 國立交通大學 |
2014-12-16T06:15:17Z |
VARIATION-TOLERANT WORD-LINE UNDER-DRIVE SCHEME FOR RANDOM ACCESS MEMORY
|
Chuang Ching-Te; Lin Yi-Wei; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:15:16Z |
ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF
|
JOU Shyh-Jye; Lin Jhih-Yu; Chuang Ching-Te; Tu Ming-Hsien; Tsai Ming-Chien |
| 國立交通大學 |
2014-12-16T06:15:14Z |
GATE OXIDE BREAKDOWN-WITHSTANDING POWER SWITCH STRUCTURE
|
YANG Hao-I; Chuang Ching-Te; Hwang Wei |
| 國立交通大學 |
2014-12-16T06:15:00Z |
INDEPENDENTY-CONTROLLED-GATE SRAM
|
CHUANG Ching-Te; Chen Yin-Nien; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin |
| 國立交通大學 |
2014-12-16T06:14:56Z |
SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION
|
Jou Shyh-Jye; Lin Jhih-Yu; Chuang Ching-Te; Tu Ming-Hsien; Chiu Yi-Wei |
| 國立交通大學 |
2014-12-16T06:14:56Z |
SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor
|
CHUANG Ching-Te; Jou Shyh-Jye; Hwang Wei; Lin Yi-Wei; Tsai Ming-Chien; Yang Hao-I; Tu Ming-Hsien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di |
| 國立交通大學 |
2014-12-16T06:14:56Z |
Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability
|
Chuang Ching-Te; Jou Shyh-Jye; Hwang Wei; Tsai Ming-Chien; Lin Yi-Wei; Yang Hao-I; Tu Ming-Hsien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di |
| 國立交通大學 |
2014-12-16T06:14:50Z |
CONTROL CIRCUIT OF SRAM AND OPERATING METHOD THEREOF
|
CHUANG Ching-Te; LIEN Nan-Chun; LIAO Wei-Nan; CHU Li-Wei; CHANG Chi-Shin; TU Ming-Hsien |
| 國立交通大學 |
2014-12-16T06:14:49Z |
STATIC RANDOM ACCESS MEMORY WITH RIPPLE BIT LINES/SEARCH LINES FOR IMROVING CURRENT LEAKAGE/VARIATION TOLERANCE AND DENSITY/PERFORMANCE
|
CHUANG Ching-Te; YANG Hao-I; LU Chien-Yu; CHEN Chien-Hen; CHANG Chi-Shin; HUANG Po-Tsang; LAI Shu-Lin; HWANG Wei; JOU Shyh-Jye; TU Ming-Hsien |
| 國立交通大學 |
2014-12-16T06:14:19Z |
High load driving device
|
Chuang Ching-Te; Lu Chien-Yu |
| 國立交通大學 |
2014-12-16T06:14:14Z |
Schmitt trigger-based finFET SRAM cell
|
Chuang Ching-Te; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin |
| 國立交通大學 |
2014-12-16T06:14:13Z |
Variation-tolerant word-line under-drive scheme for random access memory
|
Chuang Ching-Te; Lin Yi-Wei; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:14:10Z |
Disturb-free static random access memory cell
|
Chuang Ching-Te; Yang Hao-I; Lin Jihi-Yu; Yang Shyh-Chyi; Tu Ming-Hsien; Hwang Wei; Jou Shyh-Jye; Lee Kun-Ti; Li Hung-Yu |
| 國立交通大學 |
2014-12-16T06:14:08Z |
Static random access memory with data controlled power supply
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Lin Yung-Wei; Lu Chien-Yu; Tu Ming-Hsien; Hwang Wei; Jou Shyh-Jye; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:14:07Z |
Data-aware dynamic supply random access memory
|
Chuang Ching-Te; Yang Hao-I; Lin Yi-Wei; Hwang Wei; Shih Wei-Chiang; Chen Chia-Cheng |
| 國立交通大學 |
2014-12-16T06:14:04Z |
Gate oxide breakdown-withstanding power switch structure
|
Yang Hao-I; Chuang Ching-Te; Hwang Wei |
| 國立交通大學 |
2014-12-16T06:13:57Z |
Threshold voltage measurement device
|
Chuang Ching-Te; Jou Shyh-Jye; Lin Geng-Cing; Wang Shao-Cheng; Lin Yi-Wei; Tsai Ming-Chien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di; Chu Jyun-Kai |
| 國立交通大學 |
2014-12-16T06:13:54Z |
Low power static random access memory
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Hwang Wei; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:13:52Z |
Single-ended SRAM with cross-point data-aware write operation
|
Jou Shyh-Jye; Lin Jhih-Yu; Chuang Ching-Te; Tu Ming-Hsien; Chiu Yi-Wei |
| 國立交通大學 |
2014-12-16T06:13:52Z |
Independently-controlled-gate SRAM
|
Chuang Ching-Te; Chen Yin-Nien; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin |
| 國立交通大學 |
2014-12-16T06:13:50Z |
Static random access memory with ripple bit lines/search lines for improving current leakage/variation tolerance and density/performance
|
Chuang Ching-Te; Yang Hao-I; Lu Chien-Yu; Chen Chien-Hen; Chang Chi-Shin; Huang Po-Tsang; Lai Shu-Lin; Hwang Wei; Jou Shyh-Jye; Tu Ming-Hsien |
| 國立交通大學 |
2014-12-16T06:13:49Z |
Oscillato based on a 6T SRAM for measuring the bias temperature instability
|
Chuang Ching-Te; Jou Shyh-Jye; Hwang Wei; Tsai Ming-Chien; Lin Yi-Wei; Yang Hao-I; Tu Ming-Hsien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di |
| 國立交通大學 |
2014-12-16T06:13:48Z |
Static memory and memory cell thereof
|
Jou Shyh-Jye; Tu Ming-Hsien; Hu Yu-Hao; Chuang Ching-Te; Chiu Yi-Wei |
| 國立交通大學 |
2014-12-16T06:13:47Z |
Static random access memory apparatus and bit-line voltage controller thereof
|
Chuang Ching-Te; Lien Nan-Chun; Liao Wei-Nan; Chang Chi-Hsin; Yang Hao-I; Hwang Wei; Tu Ming-Hsien |
| 國立交通大學 |
2014-12-13T10:52:02Z |
超高通道與解析度微大腦皮質訊號擷取系統晶片封裝的研發---子計畫三：超高通道與解析度腦神經訊號擷取電路設計佈局及功耗優化
|
莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:51:01Z |
穿隧場效電晶體及混合穿隧場效電晶體與金氧半場效電晶體的邏輯電路與靜態隨機存取記憶體之探索與評估
|
莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:49:40Z |
奈米隨機存取記憶體的長時間可靠度劣化現象分析與可容忍此劣化現象之設計
|
莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:44:37Z |
奈米互補式金氧半場效電晶體靜態隨機存取記憶體靜態雜訊邊界與負偏壓溫度效應/正偏壓溫度效應之量測與特性化電路結構設計
|
莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:41:57Z |
奈米互補式金氧半場效電晶體靜態隨機存取記憶體靜態雜訊邊界與負偏壓溫度效應/正偏壓溫度效應之量測與特性化電路結構設計
|
莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:41:48Z |
前瞻多閘極/全包覆閘極、奈米線、及穿隧場效電晶體於靜態隨機存取記憶體、邏輯、類比應用之分析與評估
|
莊景德; Chuang Ching-Te |
| 國立交通大學 |
2014-12-13T10:36:34Z |
前瞻多閘極/全包覆閘極、奈米線、及穿隧場效電晶體於靜態隨機存取記憶體、邏輯、類比應用之分析與評估
|
莊景德; Chuang Ching-Te |
