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Institution Date Title Author
臺大學術典藏 2019-10-24T07:45:21Z Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines 江介宏;JIE-HONG JIANG;Jie-Hong Roland Jiang;Chun-Hong Shih; Chun-Hong Shih; Jie-Hong Roland Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:21Z Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines 江介宏;JIE-HONG JIANG;Jie-Hong Roland Jiang;Chun-Hong Shih; Chun-Hong Shih; Jie-Hong Roland Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:21Z Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Chun-Hong Shih;Cheng-Yu Shih; Cheng-Yu Shih; Chun-Hong Shih; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:21Z Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Chun-Hong Shih;Cheng-Yu Shih; Cheng-Yu Shih; Chun-Hong Shih; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:43:08Z Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines JIE-HONG JIANG;Jie-Hong Roland Jiang;Chun-Hong Shih; Chun-Hong Shih; Jie-Hong Roland Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:08Z Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines JIE-HONG JIANG;Jie-Hong Roland Jiang;Chun-Hong Shih; Chun-Hong Shih; Jie-Hong Roland Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:08Z Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits JIE-HONG JIANG;Jie-Hong R. Jiang;Chun-Hong Shih;Cheng-Yu Shih; Cheng-Yu Shih; Chun-Hong Shih; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:08Z Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits JIE-HONG JIANG;Jie-Hong R. Jiang;Chun-Hong Shih;Cheng-Yu Shih; Cheng-Yu Shih; Chun-Hong Shih; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2018-09-10T15:26:17Z SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis Chun-Hong Shih;Yi-Hsiang Lai;Jie-Hong R. Jiang; Chun-Hong Shih; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2018-09-10T15:26:17Z SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis Chun-Hong Shih;Yi-Hsiang Lai;Jie-Hong R. Jiang; Chun-Hong Shih; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG

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