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Showing items 1-9 of 9  (1 Page(s) Totally)
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Institution Date Title Author
中原大學 2010-05 A Post-Processing Approach to Minimize TSV Number for High-Level Synthesis of 3D ICs Chih-Hung Lee;Tsorng-Yu Huang;Chun-Hua Cheng;Shih-Hsu Huang
中原大學 2009-11 Synthesis of Anti-Aging Gated Clock Designs Shih-Hsu Huang; Chun-Hua Cheng; Song-Bin Pan
中原大學 2009-11 Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization Shih-Hsu Huang; Chun-Hua Cheng; Da-Chen Tzeng
中原大學 2009-08-19 高速度低功率非零時序差異電路之資源繫結問題研究 程駿華; Chun-Hua Cheng
中原大學 2009-08 Minimum-Period Register Binding Shih-Hsu Huang; Chun-Hua Cheng
中原大學 2009-07-25 An ILP Approach to Surge Current Minimization in High-Level Synthesis Shih-Hsu Huang; Jheng-Fu Yeh; Chun-Hua Cheng
中原大學 2009-06 Post-Floorplan Power Distribution Network Design for 3D ICs Yalamandala Raghu;Chun-Hua Cheng;Shih-Hsu Huang
中原大學 2009-05 MINIMUM-POWER CLOCK GATING Jia-Hong Jian; Chun-Hua Cheng; Chia-Ming Chang; Shih-Hsu Huang
中原大學 2005-07-19 鬆弛時間最佳化之運算排序 程駿華; Chun-Hua Cheng

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