臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
元智大學	Sep-16	Area-aware Decomposition for Single-Electron Transistor Arrays	陳勇志; Ching-Hsuan Ho; Chun-Yao Wang; Ching-Yi Huang; Suma Datta; Vijaykrishnan Narayanan
元智大學	Oct-20	LOOPLock : LOgic OPtimization based Cyclic Logic Locking	陳勇志; Hsiao-Yu Chiang; De-Xuan Ji; Xiang-Min Yang; Chia-Chun Lin; Chun-Yao Wang
元智大學	Oct-16	Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks	陳勇志; Chen-Yu Lin; Chun-Yao Wang; Ching-Yi Huang; Chiou-Ting Hsu
元智大學	Oct-16	Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks	陳勇志; Chen-Yu Lin; Chun-Yao Wang; Ching-Yi Huang; Chiou-Ting Hsu
元智大學	Jun-16	Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays	陳勇志; Ching-Yi Huang; Yun-Jui Li; Chian-Wei Liu; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
元智大學	Jun-16	Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays	陳勇志; Ching-Yi Huang; Yun-Jui Li; Chian-Wei Liu; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
元智大學	Dec-20	A New Necessary Condition for Threshold Function Identification	Chia-Chun Lin; Chin-Heng Liu; Chun-Yao Wang; 陳勇志
元智大學	Dec-19	Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments	陳勇志; Chin-Heng Liu; Chia-Chun Lin; Chia-Cheng Wu; Chun-Yao Wang; Shigeru Yamashita
元智大學	Dec-18	On Synthesizing Memristor-Based Logic Circuits with Minimal Operational Pulses	陳勇志; Hsin-Pei Wang; Chia-Chun Lin; Chia-Cheng Wu; Chun-Yao Wang
元智大學	Dec-15	Synthesis for Width Minimization in the Single-Electron Transistor Array	陳勇志; Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan

Showing items 1-10 of 54 (6 Page(s) Totally)
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