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Institution	Date	Title	Author
元智大學	Sep-16	Area-aware Decomposition for Single-Electron Transistor Arrays	陳勇志; Ching-Hsuan Ho; Chun-Yao Wang; Ching-Yi Huang; Suma Datta; Vijaykrishnan Narayanan
元智大學	Oct-20	LOOPLock : LOgic OPtimization based Cyclic Logic Locking	陳勇志; Hsiao-Yu Chiang; De-Xuan Ji; Xiang-Min Yang; Chia-Chun Lin; Chun-Yao Wang
元智大學	Oct-16	Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks	陳勇志; Chen-Yu Lin; Chun-Yao Wang; Ching-Yi Huang; Chiou-Ting Hsu
元智大學	Oct-16	Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks	陳勇志; Chen-Yu Lin; Chun-Yao Wang; Ching-Yi Huang; Chiou-Ting Hsu
元智大學	Jun-16	Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays	陳勇志; Ching-Yi Huang; Yun-Jui Li; Chian-Wei Liu; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
元智大學	Jun-16	Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays	陳勇志; Ching-Yi Huang; Yun-Jui Li; Chian-Wei Liu; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
元智大學	Dec-20	A New Necessary Condition for Threshold Function Identification	Chia-Chun Lin; Chin-Heng Liu; Chun-Yao Wang; 陳勇志
元智大學	Dec-19	Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments	陳勇志; Chin-Heng Liu; Chia-Chun Lin; Chia-Cheng Wu; Chun-Yao Wang; Shigeru Yamashita
元智大學	Dec-18	On Synthesizing Memristor-Based Logic Circuits with Minimal Operational Pulses	陳勇志; Hsin-Pei Wang; Chia-Chun Lin; Chia-Cheng Wu; Chun-Yao Wang
元智大學	Dec-15	Synthesis for Width Minimization in the Single-Electron Transistor Array	陳勇志; Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
元智大學	Dec-15	Synthesis for Width Minimization in the Single-Electron Transistor Array	陳勇志; Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
元智大學	Apr-21	Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model	陳勇志; Chia-Cheng Wu; Yi-Hsiang Hu; Chia-Chun Lin; Juinn-Dar Huang; Chun-Yao Wang
元智大學	Apr-17	Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays	陳勇志; Yun-Jui Li; Ching-Yi Huang; Chia-Cheng Wu; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
元智大學	Apr-15	Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits	陳勇志; Ching-Yi Huang; Zheng-Shan Yu; Tung-Chen Tsou; Chun-Yao Wang
元智大學	2021/1/18	A General Equivalence Checking Framework for Multivalued Logic	陳勇志; Chia-Chun Lin; Hsin-Ping Yen; Sheng-Hsiu Wei; Pei-Pei Chen; Chun-Yao Wang
元智大學	2021/1/18	A General Equivalence Checking Framework for Multivalued Logic	陳勇志; Chia-Chun Lin; Hsin-Ping Yen; Sheng-Hsiu Wei; Pei-Pei Chen; Chun-Yao Wang
元智大學	2021/1/18	An Efficient Approximate Node Merging with an Error Rate Guarantee	陳勇志; Kit Seng Tam; Chia-Chun Lin; Chun-Yao Wang
元智大學	2020/9/8	A Dynamic Expansion Order Algorithm for the SAT-based Minimization	陳勇志; Chia-Chun Lin; Kit Seng Tam; Chang-Cheng Ko; Hsin-Ping Yen; Sheng-Hsiu Wei; Chun-Yao Wang
元智大學	2020/9/8	A Dynamic Expansion Order Algorithm for the SAT-based Minimization	陳勇志; Chia-Chun Lin; Kit Seng Tam; Chang-Cheng Ko; Hsin-Ping Yen; Sheng-Hsiu Wei; Chun-Yao Wang
元智大學	2020/3/9	A Convolutional Result Sharing Approach for Binarized Neural Network Inference	陳勇志; Ya-Chun Chang; Chia-Chun Lin; Yi-Ting Lin; Chun-Yao Wang
元智大學	2020/3/9	A Convolutional Result Sharing Approach for Binarized Neural Network Inference	陳勇志; Ya-Chun Chang; Chia-Chun Lin; Yi-Ting Lin; Chun-Yao Wang
元智大學	2020/3/25	Rehabilitation System for Limbs using IMUs	陳勇志; Chun-Jui Chen; Yi-Ting Lin; Chia-Chun Lin; Yun-Ju Lee; Chun-Yao Wang
元智大學	2020/3/25	IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement	陳勇志; Teng-Chia Wang; Yan-Ping Chang; Chun-Jui Chen; Yun-Ju Lee; Chia-Chun Lin; Chun-Yao Wang
元智大學	2020/3/25	Rehabilitation System for Limbs using IMUs	陳勇志; Chun-Jui Chen; Yi-Ting Lin; Chia-Chun Lin; Yun-Ju Lee; Chun-Yao Wang
元智大學	2019-09-03	A Glitch Key-Gate for Logic Locking	陳勇志; De-Xuan Ji; Hsiao-Yu Chiang; Chia-Chun Lin; Chia-Cheng Wu; Chun-Yao Wang
元智大學	2019-09-03	A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises	陳勇志; Yan-Ping Chang; Teng-Chia Wang; Yun-Ju Lee; Chia-Chun Lin; Chun-Yao Wang
元智大學	2018-04-16	Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking	Wei-An Ji; Chih-Chung Wang; Ching-Yi Huang; Chia-Cheng Wu; Chia-Chun Lin; Chun-Yao Wang; 陳勇志
元智大學	2018-04-16	Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking	Wei-An Ji; Chih-Chung Wang; Ching-Yi Huang; Chia-Cheng Wu; Chia-Chun Lin; Chun-Yao Wang; 陳勇志
元智大學	2018-03-19	Logic Optimization with Considering Boolean Relations	陳勇志; Tung-Yuan Lee; Chia-Cheng Wu; Chia-Chun Lin; Chun-Yao Wang
元智大學	2018-03-19	Efficient Synthesis of Approximate Threshold Logic Circuits with an Error Rate Guarantee	陳勇志; Yung-An Lai; Chia-Chun Lin; Chia-Cheng Wu; Chun-Yao Wang
元智大學	2017-03-14	In&Out: Restructuring for Threshold Logic Network Optimization	陳勇志; Chia-Chun Lin; Chiao-Wei Huang; Chun-Yao Wang
元智大學	2016-01-25	MajorSat: A SAT Solver to Majority Logic	陳勇志; Yu-Min Cho; Chun-Yao Wang; Ching-Yi Huang
元智大學	2015-09-08	Synthesis and Verification of Cyclic Combinational Circuits	陳勇志; Jui-Hung Chen; Wan-Chen Weng; Ching-Yi Huang; Chun-Yao Wang
元智大學	2015-03-16	Using Range-Equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking	陳勇志; Wei-An Ji; Chih-Chung Wang; Ching-Yi Huang; Chun-Yao Wang
元智大學	2015-03-16	Using Range-Equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking	陳勇志; Wei-An Ji; Chih-Chung Wang; Ching-Yi Huang; Chun-Yao Wang
元智大學	2015-03-09	Using Structural Relations for Checking Combinationality of Cyclic Circuits	陳勇志; Wan-Chen Weng; Jui-Hung Chen; Ching-Yi Huang; Chun-Yao Wang
元智大學	2015-03-09	Using Structural Relations for Checking Combinationality of Cyclic Circuits	陳勇志; Wan-Chen Weng; Jui-Hung Chen; Ching-Yi Huang; Chun-Yao Wang
元智大學	2015-03-09	Using Structural Relations for Checking Combinationality of Cyclic Circuits	陳勇志; Wan-Chen Weng; Jui-Hung Chen; Ching-Yi Huang; Chun-Yao Wang
元智大學	2015-01-19	A Defect-aware Approach for Mapping Reconfigurable Single-Electron Transistor Arrays	陳勇志; Ching-Yi Huang; Chian-Wei Liu; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
元智大學	2015-01-19	A Defect-aware Approach for Mapping Reconfigurable Single-Electron Transistor Arrays	陳勇志; Ching-Yi Huang; Chian-Wei Liu; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
國立臺灣師範大學	2014-10-30T09:35:09Z	Biased Random Vector Generator based on Circuit Structure	Yu-Min Kuo; heng-Hung Lin; Chun-Yao Wang; Shih-Chieh Chang; Pei-Hsin Ho
國立臺灣師範大學	2014-10-30T09:35:09Z	Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure	Yu-Min Kuo; heng-Hung Lin; Chun-Yao Wang; Shih-Chieh Chang; and Pei-Hsin Ho
國立臺灣師範大學	2014-10-30T09:35:09Z	Biased Random Vector Generator based on Circuit Structure	Yu-Min Kuo; heng-Hung Lin; Chun-Yao Wang; Shih-Chieh Chang; Pei-Hsin Ho
元智大學	2014-03-24	Rewiring for threshold logic circuit minimization	陳勇志; Chia-Chun Lin; Chun-Yao Wang; Ching-Yi Huang
元智大學	2014-03-24	Width Minimization in the Single-Electron Transistor Array Synthesis	陳勇志; Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan
元智大學	2013-11-18	Sensitization Criterion for Threshold Logic Circuits and its Application	陳勇志; Chen-Kuan Tsai; Chun-Yao Wang; Ching-Yi Huang
元智大學	2013-11-18	Sensitization Criterion for Threshold Logic Circuits and its Application	陳勇志; Chen-Kuan Tsai; Chun-Yao Wang; Ching-Yi Huang
元智大學	2013-10-1	Verification of Reconfigurable Binary Decision Diagram-based Single-Electron Transistor Arrays	陳勇志; Chun-Yao Wang; Ching-Yi Huang
元智大學	2013-10-1	Verification of Reconfigurable Binary Decision Diagram-based Single-Electron Transistor Arrays	陳勇志; Chun-Yao Wang; Ching-Yi Huang
元智大學	2013-05-19	Pattern Generation for Mutation Analysis Using Genetic Algorithms	陳勇志; Yen-Chi Yang; Chun-Yao Wang; Ching-Yi Huang

Showing items 1-50 of 54 (2 Page(s) Totally)
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