| 國立交通大學 |
2014-12-16T06:15:38Z |
Digital Loop Filter for All-Digital Phase-Locked Loop Design
|
Lee, Chen-yi; Chung, Ching-che |
| 國立交通大學 |
2014-12-08T15:47:32Z |
An All Digital Spread Spectrum Clock Generator with Programmable Spread Ratio for SoC Applications
|
Sheng, Duo; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:33:45Z |
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications
|
Sheng, Duo; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:29:35Z |
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications
|
Chung, Ching-Che; Yu, Jui-Yuan; Jang, Shiou-Ru; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:28:14Z |
A Low-Power DCO Using Interlaced Hysteresis Delay Cells
|
Yu, Chien-Ying; Chung, Ching-Che; Yu, Chia-Jung; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:25:07Z |
An all-digital delay-locked loop for DDR SDRAM controller applications
|
Chung, Ching-Che; Chen, Pao-Lung; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:25:07Z |
An all-digital phase-locked loop with high-resolution for SoC applications
|
Sheng, Duo; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:25:04Z |
A fast-lock-in ADPLL with high-resolution and low-power DCO for SoC applications
|
Sheng, Duo; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:24:57Z |
Design of a 125 mu W, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications
|
Liu, Tsu-Ming; Chung, Ching-Che; Lee, Chen-Yi; Lin, Ting-An; Wang, Sheng-Zen |
| 國立交通大學 |
2014-12-08T15:13:09Z |
An ultra-low-power and portable digitally controlled oscillator for SoC applications
|
Sheng, Duo; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:10:57Z |
A symbol-rate timing synchronization method for low power wireless OFDM systems
|
Yu, Jui-Yuan; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:10:14Z |
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems
|
Yu, Jui-Yuan; Chen, Juinn-Ting; Yang, Mei-Hui; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:06:54Z |
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications
|
Sheng, Duo; Chung, Ching-Che; Lee, Chen-Yi |
| 國立高雄第一科技大學 |
2006.06 |
A Clock Generation with Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications
|
Chen, Pao-Lung;Chung, Ching-Che;Yang, Jyh-Neng;Lee, Chen-Yi |
