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Taiwan Academic Institutional Repository >
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"chung cp"
Showing items 26-35 of 69 (7 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:40:53Z |
Variable-size data item placement for load and storage balancing
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Ma, YC; Chiu, JC; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:40:52Z |
3-disjoint gamma interconnection networks
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Chen, CW; Lu, NP; Chung, CP |
| 國立交通大學 |
2014-12-08T15:40:44Z |
An inverted file cache for fast information retrieval
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Shieh, WY; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:38:46Z |
A software/hardware cooperated stack operations folding model for Java processors
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Ton, LR; Chang, LC; Shann, JJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:37:20Z |
Branch-and-bound task allocation with task clustering-based pruning
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Ma, YC; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:59Z |
ANALYZING CACHE PERFORMANCE ON MULTI-STREAM EXECUTION PROCESSOR
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LIN, CZ; TSENG, CC; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:27:37Z |
Register renaming for x86 superscalar design
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Liu, CC; Shiu, RM; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:30Z |
Instruction cache prefetching with extended BTB
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Chi, SA; Shiu, RM; Chiu, JC; Chang, SE; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:25Z |
Instruction folding in Java processor
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Ton, LR; Chang, LC; Rao, MF; Tseng, HM; Shang, SS; Ma, RL; Wang, DC; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:03Z |
Design of instruction stream buffer with trace support for x86 processors
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Chiu, JC; Huang, IH; Chung, CP |
Showing items 26-35 of 69 (7 Page(s) Totally)
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