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Taiwan Academic Institutional Repository >
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"chung cp"
Showing items 11-35 of 69 (3 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:46:15Z |
Instruction cache prefetching directed by branch prediction
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Chiu, JC; Shiu, RM; Chi, SA; Chung, CP |
| 國立交通大學 |
2014-12-08T15:46:07Z |
Reducing memory traffic and accelerating prolog execution in a superscalar prolog system
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Ma, RL; Chung, CP |
| 國立交通大學 |
2014-12-08T15:45:55Z |
Exploiting Java bytecode parallelism by enhanced POC folding model
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Ton, LR; Chang, LC; Chung, CP |
| 國立交通大學 |
2014-12-08T15:45:37Z |
Fault-tolerant gamma interconnection networks by chaining
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Chen, CW; Lu, NP; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:45:16Z |
Applying stack simulation for branch target buffers
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Shiu, RM; Lu, NP; Chung, CP |
| 國立交通大學 |
2014-12-08T15:44:41Z |
Enhancing Java processor performance with smart dynamic folding
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Chang, LC; Ton, LR; Kao, MF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:43:55Z |
High-bandwidth x86 instruction fetching based on instruction pointer table
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Chiu, JC; Chung, CP |
| 國立交通大學 |
2014-12-08T15:43:32Z |
Fault-tolerant gamma interconnection network without backtracking
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Chen, CW; Chung, CP |
| 國立交通大學 |
2014-12-08T15:43:27Z |
A dominance relation enhanced branch-and-bound task allocation
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Ma, YC; Chung, CP |
| 國立交通大學 |
2014-12-08T15:43:00Z |
Code compression techniques using operand field remapping
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Lin, K; Chung, CP |
| 國立交通大學 |
2014-12-08T15:42:28Z |
Design of instruction address queue for high degree x86 superscalar architectures
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Chiu, JC; Wang, MJY; Chung, CP |
| 國立交通大學 |
2014-12-08T15:42:04Z |
Posting file partitioning and parallel information retrieval
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Ma, YC; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:42:02Z |
An analytical POC stack operations folding for continuous and discontinuous Java bytecodes
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Ton, LR; Chang, LC; Chung, CP |
| 國立交通大學 |
2014-12-08T15:41:45Z |
Design of an optimal folding mechanism for Java processors
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Ton, LR; Chang, LC; Shann, JJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:41:27Z |
Inverted file compression through document identifier reassignment
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Shieh, WY; Chen, TF; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:40:53Z |
Variable-size data item placement for load and storage balancing
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Ma, YC; Chiu, JC; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:40:52Z |
3-disjoint gamma interconnection networks
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Chen, CW; Lu, NP; Chung, CP |
| 國立交通大學 |
2014-12-08T15:40:44Z |
An inverted file cache for fast information retrieval
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Shieh, WY; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:38:46Z |
A software/hardware cooperated stack operations folding model for Java processors
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Ton, LR; Chang, LC; Shann, JJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:37:20Z |
Branch-and-bound task allocation with task clustering-based pruning
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Ma, YC; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:59Z |
ANALYZING CACHE PERFORMANCE ON MULTI-STREAM EXECUTION PROCESSOR
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LIN, CZ; TSENG, CC; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:27:37Z |
Register renaming for x86 superscalar design
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Liu, CC; Shiu, RM; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:30Z |
Instruction cache prefetching with extended BTB
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Chi, SA; Shiu, RM; Chiu, JC; Chang, SE; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:25Z |
Instruction folding in Java processor
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Ton, LR; Chang, LC; Rao, MF; Tseng, HM; Shang, SS; Ma, RL; Wang, DC; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:03Z |
Design of instruction stream buffer with trace support for x86 processors
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Chiu, JC; Huang, IH; Chung, CP |
Showing items 11-35 of 69 (3 Page(s) Totally)
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