|
|
???tair.name??? >
???browser.page.title.author???
|
"chung cp"???jsp.browse.items-by-author.description???
Showing items 26-35 of 69 (7 Page(s) Totally)
<< < 1 2 3 4 5 6 7 > >>
View [10|25|50] records per page
| 國立交通大學 |
2014-12-08T15:40:53Z |
Variable-size data item placement for load and storage balancing
|
Ma, YC; Chiu, JC; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:40:52Z |
3-disjoint gamma interconnection networks
|
Chen, CW; Lu, NP; Chung, CP |
| 國立交通大學 |
2014-12-08T15:40:44Z |
An inverted file cache for fast information retrieval
|
Shieh, WY; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:38:46Z |
A software/hardware cooperated stack operations folding model for Java processors
|
Ton, LR; Chang, LC; Shann, JJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:37:20Z |
Branch-and-bound task allocation with task clustering-based pruning
|
Ma, YC; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:59Z |
ANALYZING CACHE PERFORMANCE ON MULTI-STREAM EXECUTION PROCESSOR
|
LIN, CZ; TSENG, CC; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:27:37Z |
Register renaming for x86 superscalar design
|
Liu, CC; Shiu, RM; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:30Z |
Instruction cache prefetching with extended BTB
|
Chi, SA; Shiu, RM; Chiu, JC; Chang, SE; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:25Z |
Instruction folding in Java processor
|
Ton, LR; Chang, LC; Rao, MF; Tseng, HM; Shang, SS; Ma, RL; Wang, DC; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:03Z |
Design of instruction stream buffer with trace support for x86 processors
|
Chiu, JC; Huang, IH; Chung, CP |
Showing items 26-35 of 69 (7 Page(s) Totally)
<< < 1 2 3 4 5 6 7 > >>
View [10|25|50] records per page
|
