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Taiwan Academic Institutional Repository >
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"chung cp"
Showing items 31-55 of 69 (3 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:27:59Z |
ANALYZING CACHE PERFORMANCE ON MULTI-STREAM EXECUTION PROCESSOR
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LIN, CZ; TSENG, CC; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:27:37Z |
Register renaming for x86 superscalar design
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Liu, CC; Shiu, RM; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:30Z |
Instruction cache prefetching with extended BTB
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Chi, SA; Shiu, RM; Chiu, JC; Chang, SE; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:25Z |
Instruction folding in Java processor
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Ton, LR; Chang, LC; Rao, MF; Tseng, HM; Shang, SS; Ma, RL; Wang, DC; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:03Z |
Design of instruction stream buffer with trace support for x86 processors
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Chiu, JC; Huang, IH; Chung, CP |
| 國立交通大學 |
2014-12-08T15:26:35Z |
Code compression by register operand dependency
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Lin, K; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:26:14Z |
A statistics-based approach to incrementally update inverted files
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Shieh, WY; Chung, CP |
| 國立交通大學 |
2014-12-08T15:26:14Z |
A tree-based inverted file for fast ranked-document retrieval
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Shieh, WY; Chen, TF; Chung, CP |
| 國立交通大學 |
2014-12-08T15:25:51Z |
A unique-order interpolative code for fast querying and space-efficient indexing in information retrieval systems
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Cheng, CS; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:25:38Z |
Low-power BIBITS encoding with register relabeling for instruction bus
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Cheng, CT; Chiao, WH; Shann, JJJ; Chung, CP; Chen, WF |
| 國立交通大學 |
2014-12-08T15:25:28Z |
Low-power data address bus encoding method
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Weng, TH; Chiao, WH; Shann, JJJ; Chung, CP; Lu, J |
| 國立交通大學 |
2014-12-08T15:25:28Z |
Low-power branch prediction
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Hu, YC; Chiao, WH; Shann, JJJ; Chung, CP; Chen, WF |
| 國立交通大學 |
2014-12-08T15:19:35Z |
A statistics-based approach to incrementally update inverted files
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Shieh, WY; Chung, CP |
| 國立交通大學 |
2014-12-08T15:18:20Z |
Designing a disjoint paths interconnection network with fault tolerance and collision solving
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Chen, CW; Chung, CP |
| 國立交通大學 |
2014-12-08T15:17:20Z |
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems
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Cheng, CS; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:16:46Z |
Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems
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Cheng, CS; Chung, CP; Shann, JJJ |
| 國立交通大學 |
2014-12-08T15:05:24Z |
DUAL-ALU CRISC ARCHITECTURE AND ITS COMPILING TECHNIQUE
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CHOU, HC; CHUNG, CP; CHENG, SC |
| 國立交通大學 |
2014-12-08T15:04:57Z |
A BOUND ANALYSIS OF SCHEDULING INSTRUCTIONS ON PIPELINED PROCESSORS WITH A MAXIMAL DELAY OF ONE CYCLE
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CHOU, HC; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:04:55Z |
ADOPTABILITY AND EFFECTIVENESS OF MICROCODE COMPACTION ALGORITHMS IN SUPERSCALAR PROCESSING
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SHIAU, YH; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:04:42Z |
MODELING OF SUPERSCALAR INSTRUCTION SCHEDULING AND ANALYSIS OF A HEURISTIC SCHEDULING ALGORITHM
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CHOU, HC; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:04:28Z |
REACHING APPROXIMATE AGREEMENT ON HYPERCUBE
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CHENG, RL; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:04:06Z |
BENCHMARKING AND ANALYSIS OF SUPERSCALAR ARCHITECTURE
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SHIAU, YH; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:04:04Z |
OPTIMAL MULTIPROCESSOR TASK-SCHEDULING USING DOMINANCE AND EQUIVALENCE-RELATIONS
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CHOU, HC; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:03:38Z |
ON THE UPPER BOUND OF SCHEDULING INSTRUCTIONS ON PIPELINED PROCESSORS WITH DELAY
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CHOU, HC; CHUNG, CP |
| 國立交通大學 |
2014-12-08T15:03:35Z |
Periodic adaptive branch prediction and its application in superscalar processing in Prolog
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Ma, RL; Chung, CP |
Showing items 31-55 of 69 (3 Page(s) Totally)
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