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Showing items 76-85 of 112  (12 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2018-09-10T04:59:54Z LARTTE: A Posynomial-Based Lagrangian Relaxation Tuning Tool for Fast and Effective Gate-Sizing and Multiple Vt Assignment Hsinwei Chou; Yu-Hao Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:54Z A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:54Z HiSIM: Hierarchical Interconnect-Centric Circuit Simulator Tsung-Hao Chen; Jeng-Liang Tsai; Charlie Chung-Ping Chen; Tanay Karnik; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:53Z Thermal and Power Integrity based Power/Ground Networks Optimization Ting-Yuan Wang; Jeng-Liang Tsai; Charlie Chung-Ping Chen; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:53Z SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis based on Model Reduction Ting-Yuan Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:53Z ESPRIT: A Compact Reluctance Based Interconnect Model Considering Lossy Substrate Eddy Current Rong Jiang; Charlie Chung-Ping Chen; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:53Z Statistical Timing Analysis in Sequential Circuit for On-Chip Global Interconnect Pipelining Lizheng Zhang; Yu Hen Hu; Charlie Chung-Ping Chen; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:52Z HiPRIME: Hierarchical and Passivity Preserved Interconnect Macromodeling Engine for RLKC Power Delivery Yu-Min Lee; Yahong Cao; Tsung-Hao Chen; Janet Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:52Z Zero-Skew Clock-Tree Optimization with Buffer-Insertion/Sizing and Wire-Sizing Jeng-Laing Tsai; Tsung-Hao Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN
臺大學術典藏 2018-09-10T04:59:52Z Wave-pipelined On-Chip Global Interconnect Lizheng Zhang; Yuhen Hu; Charlie Chung-Ping Chen; CHUNG-PING CHEN

Showing items 76-85 of 112  (12 Page(s) Totally)
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