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"chung ping chen"的相關文件
顯示項目 26-35 / 112 (共12頁)
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| 臺大學術典藏 |
2020-06-11T06:45:56Z |
High-accuracy waveguide leaky-mode analysis using a multidomain pseudospectral frequency-domain method incorporated with stretched coordinate PML
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Wang, C.-Y.;Liu, H.-H.;Chung, S.-Y.;Teng, C.-H.;Chen, C.-P.;Chang, H.-C.; Wang, C.-Y.; Liu, H.-H.; Chung, S.-Y.; Teng, C.-H.; Chen, C.-P.; Chang, H.-C.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:55Z |
The compatibility analysis of thread migration and DVFS in multi-core processor
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Oh, D.;Chen, C.C.P.;Kim, N.;Hu, Y.H.; Oh, D.; Chen, C.C.P.; Kim, N.; Hu, Y.H.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:55Z |
Interconnect delay and slew metrics using the extreme value distribution
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Zeng, J.-K.;Chen, C.-P.; Zeng, J.-K.; Chen, C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:54Z |
A fast-settling high linearity auto gain control for broadband OFDM-based PLC system
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Wu, K.-I.;Hung, S.-Y.;Hung, S.-H.;Chen, C.C.-P.; Wu, K.-I.; Hung, S.-Y.; Hung, S.-H.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:53Z |
A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS
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Cheng, W.-S.;Hsieh, M.-H.;Hung, S.-H.;Hung, S.-Y.;Chen, C.C.-P.; Cheng, W.-S.; Hsieh, M.-H.; Hung, S.-H.; Hung, S.-Y.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:53Z |
A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system
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Hung, S.-Y.;Chan, K.-H.;Chen, C.C.-P.; Hung, S.-Y.; Chan, K.-H.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:53Z |
Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation
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Wu, K.-I.;Hung, S.-H.;Shieh, S.-Y.;Hwang, B.-T.;Hung, S.-Y.;Chen, C.C.-P.; Wu, K.-I.; Hung, S.-H.; Shieh, S.-Y.; Hwang, B.-T.; Hung, S.-Y.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:53Z |
A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme
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Chien, A.;Hung, S.-H.;Wu, K.-I.;Liu, C.-Y.;Hsieh, M.-H.;Chen, C.C.-P.; Chien, A.; Hung, S.-H.; Wu, K.-I.; Liu, C.-Y.; Hsieh, M.-H.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:53Z |
A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique
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Hung, S.-H.;Kao, W.-H.;Wu, K.-I.;Huang, Y.-W.;Hsieh, M.-H.;Chen, C.C.-P.; Hung, S.-H.; Kao, W.-H.; Wu, K.-I.; Huang, Y.-W.; Hsieh, M.-H.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:52Z |
A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique
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Wang, Y.-S.;Hsieh, M.-H.;Liu, C.-M.;Wu, Y.-C.;Lin, B.-F.;Chiu, H.-C.;Chen, C.C.-P.; Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Wu, Y.-C.; Lin, B.-F.; Chiu, H.-C.; Chen, C.C.-P.; CHUNG-PING CHEN |
顯示項目 26-35 / 112 (共12頁)
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