| 臺大學術典藏 |
2020-06-11T06:45:46Z |
Frequency hopping and parallel driving with random delay especially suitable for the charger noise problem in mutual-capacitive touch applications
|
Huang, S.-L.;Hung, S.-Y.;Chen, C.-P.; Huang, S.-L.; Hung, S.-Y.; Chen, C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:45:45Z |
A significant multi-touch algorithm for the tracking problem based on the Hungarian algorithm
|
Huang, S.-L.;Chen, C.C.-P.; Huang, S.-L.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2019-10-17T00:28:48Z |
Musical Tension over Time: Listeners’ Physiological Responses to the ‘Retransition’ in Classical Sonata Form
|
CHUNG-PING CHEN;CHEN-GIA TSAI; CHEN-GIA TSAI; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T08:16:34Z |
Arachidin-1, a peanut stilbenoid, induces programmed cell death in human leukemia HL-60 cells
|
Huang, C.-P.;Au, L.-C.;Chiou, R.Y.-Y.;Chung, P.-C.;Chen, S.-Y.;Tang, W.-C.;Chang, C.-L.;Fang, W.-H.;Lin, S.-B.; Huang, C.-P.; Au, L.-C.; Chiou, R.Y.-Y.; Chung, P.-C.; Chen, S.-Y.; Tang, W.-C.; Chang, C.-L.; Fang, W.-H.; Lin, S.-B.; WOEI-HORNG FANG; CHUNG, PING-CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
Spec-based Repeater Insertion and Wire-Sizing for On-chip Interconnect
|
N. Menezes; Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation
|
Chung-Ping Chen; Chris C. N. Chu; D. F. Wong; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Noise-Aware Repeater Insertion and Wire-Sizing for On-chip Interconnect Using Hierarchical Moment-Matching
|
Chung-Ping Chen; N. Menezes; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Error-bounded Pade Approximation via Bilinear Conformal Transformation
|
Chung-Ping Chen; D.F. Wong; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:25Z |
Statistical Timing Analysis Driven Post-Silicon-Tunable Clock-Tree Synthesis
|
Jeng-Liang Tsai; Lizheng Zhang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:25Z |
ConvexFit: An Optimal Minimum-Error Convex Fitting and Smoothing Algorithm with Application to Gate-Sizing
|
Sanghamitra Roy; Weijen Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:25Z |
Efficient Statistical Capacitance Variability Modeling with Orthogonal Principle Factor Analysis
|
Rong Jiang,; Wenyin Fu,; Janet Meiling Wang,; Charlie Chung-Ping Chen,; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:25Z |
Linear Time Capacitance Extraction based on Implicit Congruence Transformation
|
Rong Jiang; Yu-hao Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:24Z |
Substrate-Bias Optimized 0.18um 2.5 GHz 32-bit adder with Post-Manufacture Tunable Clock
|
Qi-Wei Kuo; Vikas Sharma; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:24Z |
1-V 7-mW Dual-Band Fast-Locked Frequency Synthesizer
|
CHUNG-PING CHEN; Vikas Sharma,; Chien-Liang Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:24Z |
ICCAP: A Linear Time Sparse Transformation and Reordering Algorithm for 3D BEM Capacitance Extraction
|
Rong Jiang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:24Z |
Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model
|
Lizheng Zhang; Weijen Chen; Yuhen Hu; John A. Gubner; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:23Z |
Wave-Pipelined On-Chip Global Interconnect
|
Lizheng Zhang; Yu-Hen Hu; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:23Z |
Comprehensive Frequency Dependent Interconnect Extraction and Evaluction Methodology
|
CHUNG-PING CHEN; Charlie Chung-Ping Chen; Rong Jiang |
| 臺大學術典藏 |
2018-09-10T05:29:23Z |
Fast and Effective Gate-Sizing with Multiple-Vt Assignment using Generalized Lagrangian Relaxation
|
Hsinwei Chou; Yu-Hao Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:23Z |
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
|
Lizheng Zhang; Weijen Chen; Yu-Hen Hu; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:22Z |
EPEEC: A Compact Eddy-Current-Aware Reluctance-Based Macromodel for High-Speed Interconnects above Lossy Multilayer Substrate
|
Rong Jiang,; Wenyin Fu,; Charlie Chung-Ping Chen,; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:22Z |
Statistical Static Timing Analysis with Conditional Linear MAX/MIN Approximation and Extended Canonical Model
|
Lizheng Zhang; Weijen Chen; Yuhen Hu; Charlie Chungping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T05:29:22Z |
False Path and Clock Scheduling Based Yield-Aware Gate Sizing
|
Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:54Z |
Statistical Timing Analysis with AMECT: Asymptotic MAX/MIN Approximation and Extended Canonical Timing Model
|
Lizheng Zhang; Yu-Hen Hu; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:54Z |
A ROBDD-Based Generalized Nodal Control Scheme for Standby Leakage Power Reduction
|
Hsinwei Chou; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:54Z |
LARTTE: A Posynomial-Based Lagrangian Relaxation Tuning Tool for Fast and Effective Gate-Sizing and Multiple Vt Assignment
|
Hsinwei Chou; Yu-Hao Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:54Z |
A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling
|
Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:54Z |
HiSIM: Hierarchical Interconnect-Centric Circuit Simulator
|
Tsung-Hao Chen; Jeng-Liang Tsai; Charlie Chung-Ping Chen; Tanay Karnik; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:53Z |
Thermal and Power Integrity based Power/Ground Networks Optimization
|
Ting-Yuan Wang; Jeng-Liang Tsai; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:53Z |
SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis based on Model Reduction
|
Ting-Yuan Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:53Z |
ESPRIT: A Compact Reluctance Based Interconnect Model Considering Lossy Substrate Eddy Current
|
Rong Jiang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:53Z |
Statistical Timing Analysis in Sequential Circuit for On-Chip Global Interconnect Pipelining
|
Lizheng Zhang; Yu Hen Hu; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:52Z |
HiPRIME: Hierarchical and Passivity Preserved Interconnect Macromodeling Engine for RLKC Power Delivery
|
Yu-Min Lee; Yahong Cao; Tsung-Hao Chen; Janet Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:52Z |
Zero-Skew Clock-Tree Optimization with Buffer-Insertion/Sizing and Wire-Sizing
|
Jeng-Laing Tsai; Tsung-Hao Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:52Z |
Wave-pipelined On-Chip Global Interconnect
|
Lizheng Zhang; Yuhen Hu; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:59:52Z |
Realizable Reduction for Electromagnetically Coupled RLMC Interconnects
|
Rong Jiang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:36:04Z |
The Power Grid Transient Simulation in Linear Time based on 3D Alternating-Direction-Implicit Method
|
Yu-Min Lee; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:36:04Z |
Epsilon-Optimal Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time
|
Jeng-Laing Tsai; Tsung-Hao Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:36:04Z |
PODEA: POwer Delivery Efficient Analysis with Realizable Model Reduction
|
Rong Jiang; Tsung-Hao Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:36:04Z |
3D Thermal-ADI: An Efficient Chip-Level Transient Thermal Simulator
|
CHUNG-PING CHEN; Ting-Yuan Wang, Yu-Min Lee,; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:36:03Z |
INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor
|
Tsung-Hao Chen; Clement Luk; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:36:03Z |
Thermal-ADI: A Linear-Time Chip-Level Dynamic Thermal Simulation Algorithm Based on Alternating-Direction-Implicit (ADI) Method
|
Ting-Yuan Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:36:03Z |
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
|
Tsung-Hao Chen; Clement Luk; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:15:42Z |
3-D Thermal-ADI: a linear-time chip level transient thermal simulator
|
CHUNG-PING CHEN; Ting-Yuan Wang,; Charlie Chung-Ping Chen,; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:15:42Z |
Optimal Wire-sizing Function under the Elmore Delay Model with Bounded Wiresizes
|
CHUNG-PING CHEN; Charlie Chung-Ping Chen; D. F. Wong; Yu-Min Lee |
| 臺大學術典藏 |
2018-09-10T04:15:42Z |
INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor
|
Tsung-Hao Chen; Clement Luk; Hyungsuk Kim; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:15:42Z |
HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodeling Engine for RLKC Power Delivery
|
Yahong Cao; Yu-Min Lee; Tsung-Hao Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T04:15:42Z |
Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm
|
Ting-Yuan Wang; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T03:50:58Z |
FDTD-ADI: An Unconditionally Stable Full Wave Maxwell Equation Solver for VLSI Modeling
|
Charlie Chung-Ping Chen; Narayanan Murugesan; Tae-Woo Lee; Susan C. Hagness; Yu-Min Lee; Charlie Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T03:50:58Z |
Linear Time Hierarchical Capacitance Extraction Without Multipole Expansion
|
Pradeepsunder Ganesh; Charlie Chung-Ping Chen; CHUNG-PING CHEN; Saisanthosh Balakrishnan; Jong Hyuk Park; Hyungsuk Kim; Yu-Min Lee; Charlie Chung-Ping Chen |
