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Taiwan Academic Institutional Repository >
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"chung ss"
Showing items 1-25 of 36 (2 Page(s) Totally)
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| 國立交通大學 |
2019-04-02T05:59:32Z |
A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
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Yih, CM; Cheng, SM; Chung, SS |
| 國立交通大學 |
2019-04-02T05:58:52Z |
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
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Cheng, SM; Yih, CM; Yeh, JC; Kuo, SN; Chung, SS |
| 國立交通大學 |
2014-12-08T15:49:16Z |
New insight into the degradation mechanism of nitride spacer with different post-oxide in submicron LDD n-MOSFET's
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Yih, CM; Wang, CL; Chung, SS; Wu, CC; Tan, W; Wu, HJ; Pi, S; Huang, D |
| 國立交通大學 |
2014-12-08T15:47:24Z |
A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
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Yih, CM; Cheng, SM; Chung, SS |
| 國立交通大學 |
2014-12-08T15:46:24Z |
A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's
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Chung, SS; Yang, JJ |
| 國立交通大學 |
2014-12-08T15:46:14Z |
A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles
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Chung, SS; Yih, CM; Cheng, SM; Liang, MS |
| 國立交通大學 |
2014-12-08T15:44:20Z |
New degradation mechanisms of width-dependent hot carrier effect in quarter-micron shallow-trench-isolated p-channel metal-oxide-semiconductor field-effect-transistors
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Chung, SS; Chen, SJ; Yang, WJ; Yih, CM; Yang, JJ |
| 國立交通大學 |
2014-12-08T15:44:13Z |
Characterization of hot-hole injection induced SILC and related disturbs in flash memories
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Yih, CM; Ho, ZH; Liang, MS; Chung, SS |
| 國立交通大學 |
2014-12-08T15:27:48Z |
Direct observation of the lateral nonuniform channel doping profile in submicron MOSFET's from an anomalous charge pumping measurement results
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Chung, SS; Cheng, SM; Lee, GH; Guo, JC |
| 國立交通大學 |
2014-12-08T15:27:45Z |
Accurate MOS device hot carrier models for VLSI reliability simulation
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CHUNG, SS; YANG, JJ; SU, JS |
| 國立交通大學 |
2014-12-08T15:27:35Z |
A numerical model for simulating MOSFET gate current degradation by considering the interface state generation
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Yih, CM; Chung, SS; Hsu, CCH |
| 國立交通大學 |
2014-12-08T15:27:33Z |
A physically-based built-in Spice Poly-Si TFT model for circuit simulation and reliability evaluation
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Chung, SS; Chen, DC; Cheng, CT; Yeh, CF |
| 國立交通大學 |
2014-12-08T15:27:25Z |
A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles
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Chung, SS; Yih, CM; Cheng, SM; Liang, MS |
| 國立交通大學 |
2014-12-08T15:27:23Z |
Performance and reliability evaluations of P-channel flash memories with different programming schemes
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Chung, SS; Kuo, SN; Yih, CM; Chao, TS |
| 國立交通大學 |
2014-12-08T15:27:09Z |
Universal switched-current integrator blocks for SI filter design
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Chan, JL; Chung, SS |
| 國立交通大學 |
2014-12-08T15:27:09Z |
An accurate hot carrier reliability monitor for deep-submicron shallow S/D junction thin gate oxide n-MOSFET's
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Chung, SS; Chen, SJ; Yih, CM; Yang, WJ; Chao, TS |
| 國立交通大學 |
2014-12-08T15:26:55Z |
N-channel versus P-channel flash EEPROM - Which one has better reliabilities
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Chung, SS; Liaw, ST; Yih, CM; Ho, ZH; Lin, CJ; Kuo, DS; Liang, MS |
| 國立交通大學 |
2014-12-08T15:26:48Z |
New experimental evidences of the plasma charging enhanced hot carrier effect and its impact on surface channel CMOS devices
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Chen, SJ; Lin, CC; Chung, SS; Lin, HC |
| 國立交通大學 |
2014-12-08T15:26:48Z |
A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices
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Chung, SS; Chen, SJ; Yang, WJ; Yang, JJ |
| 國立交通大學 |
2014-12-08T15:26:32Z |
A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
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Chung, SS; Chen, SJ; Yang, CK; Cheng, SM; Lin, SH; Sheng, YC; Lin, HS; Hung, KT; Wu, DY; Yew, TR; Chien, SC; Liou, FT; Wen, F |
| 國立交通大學 |
2014-12-08T15:26:27Z |
Localization of NBTI-induced oxide damage in direct tunneling regime gate oxide pMOSFET using a novel low gate-leakage gated-diode (L-2-GD) method
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Chung, SS; Lo, DK; Yang, JJ; Lin, TC |
| 國立交通大學 |
2014-12-08T15:26:23Z |
An improved interface characterization technique for a full-range profiling of oxide damage in ultra-thin gate oxide CMOS devices
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Chen, SJ; Lin, TC; Lo, DK; Yang, JJ; Chung, SS; Kao, TY; Shiue, RY; Wang, CJ; Peng, YK |
| 國立交通大學 |
2014-12-08T15:26:18Z |
A novel leakage current separation technique in a direct Tunneling regime gate oxide SONOS memory cell
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Chung, SS; Chiang, PY; Chou, G; Huang, CT; Chen, P; Chu, CH; Hsu, CCH |
| 國立交通大學 |
2014-12-08T15:26:10Z |
The performance and reliability enhancement of ETOX P-channel flash EEPROM cell with P-doped floating-gate
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Tsai, HW; Chiang, PY; Chung, SS; Kuo, DS; Liang, MS |
| 國立交通大學 |
2014-12-08T15:25:51Z |
The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology
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Chung, SS; Yeh, CH; Feng, SJ; Lai, CS; Yang, JJ; Chen, CC; Jin, Y; Chen, SC; Liang, MS |
Showing items 1-25 of 36 (2 Page(s) Totally)
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