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Taiwan Academic Institutional Repository >
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"chung ss"
Showing items 11-35 of 36 (2 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:27:35Z |
A numerical model for simulating MOSFET gate current degradation by considering the interface state generation
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Yih, CM; Chung, SS; Hsu, CCH |
| 國立交通大學 |
2014-12-08T15:27:33Z |
A physically-based built-in Spice Poly-Si TFT model for circuit simulation and reliability evaluation
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Chung, SS; Chen, DC; Cheng, CT; Yeh, CF |
| 國立交通大學 |
2014-12-08T15:27:25Z |
A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles
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Chung, SS; Yih, CM; Cheng, SM; Liang, MS |
| 國立交通大學 |
2014-12-08T15:27:23Z |
Performance and reliability evaluations of P-channel flash memories with different programming schemes
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Chung, SS; Kuo, SN; Yih, CM; Chao, TS |
| 國立交通大學 |
2014-12-08T15:27:09Z |
Universal switched-current integrator blocks for SI filter design
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Chan, JL; Chung, SS |
| 國立交通大學 |
2014-12-08T15:27:09Z |
An accurate hot carrier reliability monitor for deep-submicron shallow S/D junction thin gate oxide n-MOSFET's
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Chung, SS; Chen, SJ; Yih, CM; Yang, WJ; Chao, TS |
| 國立交通大學 |
2014-12-08T15:26:55Z |
N-channel versus P-channel flash EEPROM - Which one has better reliabilities
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Chung, SS; Liaw, ST; Yih, CM; Ho, ZH; Lin, CJ; Kuo, DS; Liang, MS |
| 國立交通大學 |
2014-12-08T15:26:48Z |
New experimental evidences of the plasma charging enhanced hot carrier effect and its impact on surface channel CMOS devices
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Chen, SJ; Lin, CC; Chung, SS; Lin, HC |
| 國立交通大學 |
2014-12-08T15:26:48Z |
A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices
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Chung, SS; Chen, SJ; Yang, WJ; Yang, JJ |
| 國立交通大學 |
2014-12-08T15:26:32Z |
A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
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Chung, SS; Chen, SJ; Yang, CK; Cheng, SM; Lin, SH; Sheng, YC; Lin, HS; Hung, KT; Wu, DY; Yew, TR; Chien, SC; Liou, FT; Wen, F |
| 國立交通大學 |
2014-12-08T15:26:27Z |
Localization of NBTI-induced oxide damage in direct tunneling regime gate oxide pMOSFET using a novel low gate-leakage gated-diode (L-2-GD) method
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Chung, SS; Lo, DK; Yang, JJ; Lin, TC |
| 國立交通大學 |
2014-12-08T15:26:23Z |
An improved interface characterization technique for a full-range profiling of oxide damage in ultra-thin gate oxide CMOS devices
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Chen, SJ; Lin, TC; Lo, DK; Yang, JJ; Chung, SS; Kao, TY; Shiue, RY; Wang, CJ; Peng, YK |
| 國立交通大學 |
2014-12-08T15:26:18Z |
A novel leakage current separation technique in a direct Tunneling regime gate oxide SONOS memory cell
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Chung, SS; Chiang, PY; Chou, G; Huang, CT; Chen, P; Chu, CH; Hsu, CCH |
| 國立交通大學 |
2014-12-08T15:26:10Z |
The performance and reliability enhancement of ETOX P-channel flash EEPROM cell with P-doped floating-gate
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Tsai, HW; Chiang, PY; Chung, SS; Kuo, DS; Liang, MS |
| 國立交通大學 |
2014-12-08T15:25:51Z |
The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology
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Chung, SS; Yeh, CH; Feng, SJ; Lai, CS; Yang, JJ; Chen, CC; Jin, Y; Chen, SC; Liang, MS |
| 國立交通大學 |
2014-12-08T15:25:49Z |
An accurate RF CMOS gate resistance model compatible with HSPICE
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Lin, HW; Chung, SS; Wong, SC; Huang, GW |
| 國立交通大學 |
2014-12-08T15:25:49Z |
Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range
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Chung, SS; Feng, HJ; Hsieh, YS; Liu, A; Lin, WM; Chen, DF; Ho, JH; Huang, KT; Yang, CK; Cheng, O; Sheng, YC; Wu, DY; Shiau, WT; Chien, SC; Liao, K; Sun, SW |
| 國立交通大學 |
2014-12-08T15:25:47Z |
Different approaches for reliability enhancement of p-channel flash memory
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Chung, SS; Chen, YJ; Tsai, AW |
| 國立交通大學 |
2014-12-08T15:25:27Z |
A new observation of the germanium outdiffusion effect on the hot carrier and NBTI reliabilities in sub-100nm technology strained-Si/SiGe CMOS devices
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Chung, SS; Liu, YR; Yeh, CF; Wu, SR; Lai, CS; Chang, TY; Ho, JH; Liu, CY; Huang, CT; Tsai, CT; Shiau, WT; Sun, SW |
| 國立交通大學 |
2014-12-08T15:25:11Z |
A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering
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Chung, SS; Liu, YR; Wu, SJ; Lai, CS; Liu, YC; Chen, DF; Lin, HS; Shiau, WT; Tsai, CT; Chien, SC; Sun, SW |
| 國立交通大學 |
2014-12-08T15:17:09Z |
Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack
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Chung, SS; Yeh, CH; Feng, HJ; Lai, CS; Yang, JJ; Chen, CC; Jin, Y; Chen, SC; Liang, MS |
| 國立交通大學 |
2014-12-08T15:03:20Z |
A NEW PROFILING TECHNIQUE FOR CHARACTERIZING HOT-CARRIER-INDUCED OXIDE DAMAGES IN LDD-N-MOSFETS
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LEE, GH; SU, JS; CHUNG, SS |
| 國立交通大學 |
2014-12-08T15:02:55Z |
A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFET's
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Lee, RGH; Su, JS; Chung, SS |
| 國立交通大學 |
2014-12-08T15:02:35Z |
An efficient method for characterizing time-evolutional interface state and its correlation with the device degradation in LDD n-MOSFET's
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Lee, RGH; Wu, JP; Chung, SS |
| 國立交通大學 |
2014-12-08T15:01:20Z |
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
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Cheng, SM; Yih, CM; Yeh, JC; Kuo, SN; Chung, SS |
Showing items 11-35 of 36 (2 Page(s) Totally)
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