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Showing items 11-20 of 36 (4 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:27:35Z |
A numerical model for simulating MOSFET gate current degradation by considering the interface state generation
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Yih, CM; Chung, SS; Hsu, CCH |
| 國立交通大學 |
2014-12-08T15:27:33Z |
A physically-based built-in Spice Poly-Si TFT model for circuit simulation and reliability evaluation
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Chung, SS; Chen, DC; Cheng, CT; Yeh, CF |
| 國立交通大學 |
2014-12-08T15:27:25Z |
A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles
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Chung, SS; Yih, CM; Cheng, SM; Liang, MS |
| 國立交通大學 |
2014-12-08T15:27:23Z |
Performance and reliability evaluations of P-channel flash memories with different programming schemes
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Chung, SS; Kuo, SN; Yih, CM; Chao, TS |
| 國立交通大學 |
2014-12-08T15:27:09Z |
Universal switched-current integrator blocks for SI filter design
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Chan, JL; Chung, SS |
| 國立交通大學 |
2014-12-08T15:27:09Z |
An accurate hot carrier reliability monitor for deep-submicron shallow S/D junction thin gate oxide n-MOSFET's
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Chung, SS; Chen, SJ; Yih, CM; Yang, WJ; Chao, TS |
| 國立交通大學 |
2014-12-08T15:26:55Z |
N-channel versus P-channel flash EEPROM - Which one has better reliabilities
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Chung, SS; Liaw, ST; Yih, CM; Ho, ZH; Lin, CJ; Kuo, DS; Liang, MS |
| 國立交通大學 |
2014-12-08T15:26:48Z |
New experimental evidences of the plasma charging enhanced hot carrier effect and its impact on surface channel CMOS devices
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Chen, SJ; Lin, CC; Chung, SS; Lin, HC |
| 國立交通大學 |
2014-12-08T15:26:48Z |
A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices
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Chung, SS; Chen, SJ; Yang, WJ; Yang, JJ |
| 國立交通大學 |
2014-12-08T15:26:32Z |
A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
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Chung, SS; Chen, SJ; Yang, CK; Cheng, SM; Lin, SH; Sheng, YC; Lin, HS; Hung, KT; Wu, DY; Yew, TR; Chien, SC; Liou, FT; Wen, F |
Showing items 11-20 of 36 (4 Page(s) Totally)
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