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Institution Date Title Author
國立交通大學 2018-08-21T05:53:03Z A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path Hsieh, E. Ray; Kuo, Yen Chen; Cheng, Chih-Hung; Kuo, Jing Ling; Jiang, Meng-Ru; Lin, Jian-Li; Chen, Hung-Wen; Chung, Steve S.; Liu, Chuan-Hsi; Chen, Tse Pu; Huang, Shih An; Chen, Tai-Ju; Cheng, Osbert
國立交通大學 2018-01-24T07:42:48Z 新穎高性能鰭式電晶體結構 及其高頻特性分析 林建里; 莊紹勳; Lin, Jian-Li; Chung, Steve-S.
國立交通大學 2018-01-24T07:42:00Z 14奈米鰭式電晶體自熱效應的新穎溫度量測方法 及其對傳輸機制之影響 江孟儒; 莊紹勳; Jiang, Meng-Ru; Chung, Steve S.
國立交通大學 2018-01-24T07:41:58Z 一種新穎的鰭式電晶體可程式神經陣列 在人工神經網路的應用 陳泓文; 莊紹勳; Chen, Hung-Wen; Chung, Steve S.
國立交通大學 2017-04-21T06:56:06Z A theoretical and experimental evaluation of surface roughness variation in trigate metal oxide semiconductor field effect transistors Hsieh, E. R.; Chung, Steve S.
國立交通大學 2017-04-21T06:50:15Z Fully CMOS Compatible 3D Vertical RRAM with Self-aligned Self-selective Cell Enabling Sub-5nm Scaling Xu, Xiaoxin; Luo, Qing; Gong, Tiancheng; Lv, Hangbing; Long, Shibing; Liu, Qi; Chung, Steve S.; Li, Jing; Liu, Ming
國立交通大學 2017-04-21T06:50:15Z A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects Hung, C. M.; Li, K. C.; Hsieh, E. R.; Wang, C. T.; Kou, C. I.; Chang, Edward Y.; Chung, Steve S.
國立交通大學 2017-04-21T06:50:15Z A New Variation Plot to Examine the Interfacial-dipole Induced Work-function Variation in Advanced High-k Metal-gate CMOS Devices Hsieh, E. R.; Wang, Y. D.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Hsu, S.
國立交通大學 2017-04-21T06:50:00Z The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T.
國立交通大學 2017-04-21T06:50:00Z The Process and Stress-Induced Variability Issues of Trigate CMOS Devices Chung, Steve S.

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