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Taiwan Academic Institutional Repository >
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"chung steve s"
Showing items 26-35 of 136 (14 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:50:15Z |
Fully CMOS Compatible 3D Vertical RRAM with Self-aligned Self-selective Cell Enabling Sub-5nm Scaling
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Xu, Xiaoxin; Luo, Qing; Gong, Tiancheng; Lv, Hangbing; Long, Shibing; Liu, Qi; Chung, Steve S.; Li, Jing; Liu, Ming |
| 國立交通大學 |
2017-04-21T06:50:15Z |
A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects
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Hung, C. M.; Li, K. C.; Hsieh, E. R.; Wang, C. T.; Kou, C. I.; Chang, Edward Y.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:50:15Z |
A New Variation Plot to Examine the Interfacial-dipole Induced Work-function Variation in Advanced High-k Metal-gate CMOS Devices
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Hsieh, E. R.; Wang, Y. D.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Hsu, S. |
| 國立交通大學 |
2017-04-21T06:50:00Z |
The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices
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Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T. |
| 國立交通大學 |
2017-04-21T06:50:00Z |
The Process and Stress-Induced Variability Issues of Trigate CMOS Devices
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Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:47Z |
The RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devices
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Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:49:45Z |
3D-TCAD Simulation Study of the Novel T-FinFET Structure for Sub-14nm Metal-Oxide-Semiconductor Field-Effect Transistor
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Chou, Chen-Han; Hsu, Chung-Chun; Chung, Steve S.; Chien, Chao-Hsin |
| 國立交通大學 |
2017-04-21T06:49:45Z |
Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power Applications
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Hsieh, E. R.; Lin, Y. S.; Zhao, Y. B.; Liu, C. H.; Chien, C. H.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:28Z |
The Impact of the Three-Dimensional Gate on the Trigate FinFETs
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Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:14Z |
A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology
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Hsieh, E. R.; Hung, C. M.; Wang, T. Y.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R. |
Showing items 26-35 of 136 (14 Page(s) Totally)
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