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Taiwan Academic Institutional Repository >
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"chung steve s"
Showing items 26-50 of 136 (6 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:50:15Z |
Fully CMOS Compatible 3D Vertical RRAM with Self-aligned Self-selective Cell Enabling Sub-5nm Scaling
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Xu, Xiaoxin; Luo, Qing; Gong, Tiancheng; Lv, Hangbing; Long, Shibing; Liu, Qi; Chung, Steve S.; Li, Jing; Liu, Ming |
| 國立交通大學 |
2017-04-21T06:50:15Z |
A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects
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Hung, C. M.; Li, K. C.; Hsieh, E. R.; Wang, C. T.; Kou, C. I.; Chang, Edward Y.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:50:15Z |
A New Variation Plot to Examine the Interfacial-dipole Induced Work-function Variation in Advanced High-k Metal-gate CMOS Devices
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Hsieh, E. R.; Wang, Y. D.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Hsu, S. |
| 國立交通大學 |
2017-04-21T06:50:00Z |
The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices
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Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T. |
| 國立交通大學 |
2017-04-21T06:50:00Z |
The Process and Stress-Induced Variability Issues of Trigate CMOS Devices
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Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:47Z |
The RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devices
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Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:49:45Z |
3D-TCAD Simulation Study of the Novel T-FinFET Structure for Sub-14nm Metal-Oxide-Semiconductor Field-Effect Transistor
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Chou, Chen-Han; Hsu, Chung-Chun; Chung, Steve S.; Chien, Chao-Hsin |
| 國立交通大學 |
2017-04-21T06:49:45Z |
Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power Applications
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Hsieh, E. R.; Lin, Y. S.; Zhao, Y. B.; Liu, C. H.; Chien, C. H.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:28Z |
The Impact of the Three-Dimensional Gate on the Trigate FinFETs
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Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:14Z |
A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology
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Hsieh, E. R.; Hung, C. M.; Wang, T. Y.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:49:09Z |
An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage Operation
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Hsieh, E. R.; Chuang, C. H.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:07Z |
Recent Advances of RTN Technique Towards the Understanding of the Gate Dielectric Reliability in Trigate FinFETs
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Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:07Z |
Experimental Techniques on the Understanding of the Charge Loss in a SONOS Nitride-storage Nonvolatile Memory
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Hsieh, E. R.; Wang, H. T.; Chung, Steve S.; Chang, Wayne; Wang, S. D.; Chen, C. H. |
| 國立交通大學 |
2017-04-21T06:49:02Z |
A Novel One Transistor Resistance-Gate Nonvolatile Memory
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Chung, Steve S.; Hsieh, E. R.; Yang, S. P.; Chuang, C. H. |
| 國立交通大學 |
2017-04-21T06:48:53Z |
The Random Dopant and Gate Oxide Variations in Trigate MOSFETs
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Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:48:48Z |
3D-TCAD Simulation Study of the Contact All Around T-FinFET Structure for 10nm Metal-Oxide-Semiconductor Field-Effect Transistor
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Chou, Chen-Han; Hsu, Chung-Chun; Yeh, Wen-Kuan; Chung, Steve S.; Chien, Chao-Hsin |
| 國立交通大學 |
2017-04-21T06:48:46Z |
A Novel One Transistor Non-volatile Memory Feasible for NOR and NAND Applications in IoT Era
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Chung, Steve S.; Hsieh, E. R.; Yang, S. P.; Chuang, C. H. |
| 國立交通大學 |
2017-04-21T06:48:32Z |
Demonstration of 3D Vertical RRAM with Ultra Low-leakage, High-selectivity and Self-compliance Memory Cells
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Luo, Qing; Xu, Xiaoxin; Liu, Hongtao; Lv, Hangbing; Gong, Tiancheng; Long, Shibing; Liu, Qi; Sun, Haitao; Banerjee, Writam; Li, Ling; Gao, Jianfeng; Lu, Nianduan; Chung, Steve S.; Li, Jing; Liu, Ming |
| 國立交通大學 |
2017-04-21T06:48:18Z |
The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown
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Hsieh, E. R.; Huang, Z. H.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:48:17Z |
High Performance Design of Tunneling FET for Low Voltage/Power Applications: Strategies and Solutions
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Chung, Steve S. |
| 國立交通大學 |
2016-03-29T00:01:14Z |
低功耗互補式穿隧場效電晶體的設計與製作 (I)
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莊紹勳; Chung Steve S |
| 國立交通大學 |
2016-03-28T08:17:32Z |
高性能先進三維閘極CMOS應變元件設計-元件至電路的考量( III )
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莊紹勳; Chung Steve S |
| 國立交通大學 |
2016-03-28T08:17:22Z |
低功耗互補式穿隧場效電晶體的設計與製作 (I)
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莊紹勳; Chung Steve S |
| 國立交通大學 |
2016-03-28T00:04:19Z |
The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement
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Hsieh, E. R.; Chung, Steve S. |
| 國立交通大學 |
2015-12-02T03:00:54Z |
The Observation of BTI-induced RTN Traps in Inversion and Accumulation Modes on HfO2 High-k Metal Gate 28nm CMOS Devices
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Wu, P. C.; Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T. |
Showing items 26-50 of 136 (6 Page(s) Totally)
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