臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T04:35:42Z	Non-Assignable Signal Support During Formal Verification Of Circuit Designs	Chung-Yang (Ric) Huang; CHUNG-YANG HUANG
臺大學術典藏	2018-09-10T04:35:41Z	A Circuit SAT Solver with Signal Correlation Guided Learning	Feng Lu; Li-C. Wang; K-T. Cheng,; Ric C-Y. Huang; CHUNG-YANG HUANG
臺大學術典藏	2018-09-10T03:50:38Z	Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking	R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG
臺大學術典藏	2018-09-10T03:50:38Z	An Analysis of ATPG and SAT algorithms for Formal Verification	G. Parthasarathy; K-T. Cheng; C-Y Huang; CHUNG-YANG HUANG
臺大學術典藏	2011-01	A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization	Shao-Lun Huang; Chi-An Wu; Kai-Fu Tang; Chang-Hong Hsu; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG
臺大學術典藏	2011	Match and replace - A functional ECO engine for multi-error circuit rectification.	Lin, Wei-Hsun; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG; Huang, Shao-Lun; Huang, Shao-Lun;Lin, Wei-Hsun;Huang, Chung-Yang (Ric)

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